Utsav Banerjee received his B.Tech. (Hons.) degree in Electronics & Electrical Communication Engineering from Indian Institute of Technology Kharagpur (Kharagpur, WB, India) in 2013, and his S.M. and Ph.D. degrees in Electrical Engineering & Computer Science from Massachusetts Institute of Technology (Cambridge, MA, USA) in 2017 and 2021 respectively. During his S.M. and Ph.D., he was a member of the Energy Efficient Circuits & Systems Group supervised by Prof. Anantha P. Chandrakasan at MIT, where he worked on the design and implementation of efficient algorithms, protocols and hardware architectures for next-generation cryptography in embedded systems. He also completed a minor in quantum and solid-state physics as part of his doctoral studies.
He was a recipient of the Kishore Vaigyanik Protsahan Yojana Fellowship in 2007, the President of India Gold Medal and Institute Silver Medal from IIT Kharagpur in 2013, the Irwin Mark Jacobs & Joan Klein Jacobs Presidential Fellowship from MIT in 2015, the Qualcomm Innovation Fellowship in 2016, the Pratiksha Trust Young Investigator Award from IISc in 2022 and the ABB Research Award in Honor of Hubertus von Grünberg in 2022.
From 2013 to 2015, he was with the Low Power System-on-Chip Design team at Qualcomm, where he was involved in the design and validation of power management architectures for next-generation Snapdragon mobile processors.
His research interest lies in the intersection of cryptography, hardware security, digital circuits and embedded systems. He has comprehensive experience in the design of efficient side-channel-secure configurable architectures for cryptographic hardware acceleration in Internet of Things (IoT) applications, including encryption, hash functions, elliptic curves, bilinear pairings, lattices, isogenies and post-quantum cryptography. This involves not only circuit and architectural techniques but also algorithmic optimizations and software-hardware co-design. He has also worked on the optimization of network security protocols and their implementation using embedded micro-processors and custom hardware platforms. He is also interested in secure privacy-preserving computation, security aspects of machine learning and quantum computing.
He has extensive experience in digital chip design, having taped out and tested multiple prototype chips as part of his doctoral research. This includes architectural definition, register transfer level design, circuit optimization, simulation, synthesis, layout, test setup and post-silicon validation.
Ph.D. Thesis: “Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems” [link]
S.M. Thesis: “Energy-Efficient Protocols and Hardware Architectures for Transport Layer Security” [link]