Chip Gallery

Hardware Accelerator ASIC Designs

Isogeny-Based SQIsign Signature Verification

Tech Node: TSMC 28nm HPC+

Ref: ISSCC 2026

Transport Layer Security with AES, SHA and ECC

Tech Node: TSMC 65nm LP

Ref: ISSCC 2018, JSSC 2019

Quantum-Safe Lattice Cryptography

Tech Node: TSMC 40nm LP

Ref: ISSCC 2019, TCHES 2019

BLS12-381 Pairing-Based Functional Encryption

Tech Node: TSMC 40nm LP

Ref: CICC 2021, SSCL 2021