Conference Publications

  1. A. Banerjee, U. Banerjee, “A High-Performance Curve25519 and Curve448 Unified Elliptic Curve Cryptography Accelerator,” IEEE High Performance Extreme Computing Conference (HPEC), September 2024. [link]
  2. K. Magar, S. Bharathan, U. Banerjee, “pc-COP: An Efficient and Configurable 2048-p-Bit Fully-Connected Probabilistic Computing Accelerator for Combinatorial Optimization,” IEEE High Performance Extreme Computing Conference (HPEC), September 2024. [link]
  3. U. Banerjee, “Energy-Efficient and Secure Clustering with Post-Quantum DTLS in Wireless Sensor Networks,” IEEE Symposium on Computers and Communications (ISCC), June 2024. [link]
  4. U. Banerjee, “Energy-Efficient Cryptographic Acceleration using Hardware-Software Co-Design with RISC-V,” IEEE International Symposium on Smart Electronic Systems (iSES), December 2023. [link]
  5. U. Banerjee, “Privacy-Preserving Edge Computing from Pairing-Based Inner Product Functional Encryption,” IEEE Global Communications Conference (GLOBECOM), December 2023. [link]
  6. Y. Jain, U. Banerjee, “Tyche: A Compact and Configurable Accelerator for Scalable Probabilistic Computing on FPGA,” IEEE High Performance Extreme Computing Conference (HPEC), September 2023. [link]
  7. E. Lee, M. I. W. Khan, X. Chen, U. Banerjee, N. M. Monroe, R. T. Yazicigil, R. Han, A. P. Chandrakasan, “A 1.54mm2 Wake-Up Receiver Based on THz Carrier Wave and Integrated Cryptographic Authentication,” IEEE Custom Integrated Circuits Conference (CICC), April 2023. [link]
  8. F. Ahsan, U. Banerjee, “Embedded Software Implementation of Privacy Preserving Matrix Computation using Elliptic Curve Cryptography for IoT Applications,” IEEE International Symposium on Advanced Networks and Telecommunication Systems (ANTS), December 2022. [link]
  9. C. Lu, U. Banerjee, K. Basu, “Design and Analysis of a Scalable and Efficient Quantum Circuit for LWE Matrix Arithmetic,” IEEE International Conference on Computer Design (ICCD), October 2022. [link]
  10. M. R. Abdelhamid, U. Ha, U. Banerjee, F. Adib, A. P. Chandrakasan, “Wireless, Batteryless, and Secure Implantable System-on-a-Chip for 1.37mmHg Strain Sensing with Bandwidth Reconfigurability for Cross-Tissue Adaptation,” IEEE Custom Integrated Circuits Conference (CICC), April 2022. [link]
  11. S. Maji, U. Banerjee, S. H. Fuller, A. P. Chandrakasan, “A Threshold Implementation-Based Neural Network Accelerator Securing Model Parameters and Inputs Against Power Side-Channel Attacks,” IEEE International Solid-State Circuits Conference (ISSCC), February 2022. [link]
  12. S. Maji, U. Banerjee, S. H. Fuller, R. T. Yazicigil, A. P. Chandrakasan, “Securing Embedded Medical Devices using Dual-Factor Authentication,” IEEE International Symposium on Computer-Based Medical Systems (CBMS), June 2021. [link]
  13. U. Banerjee, A. P. Chandrakasan, “A Low-Power Elliptic Curve Pairing Crypto-Processor for Secure Embedded Blockchain and Functional Encryption,” IEEE Custom Integrated Circuits Conference (CICC), April 2021. [link]
  14. U. Banerjee, S. Das, A. P. Chandrakasan, “Accelerating Post-Quantum Cryptography using an Energy-Efficient TLS Crypto-Processor,” IEEE International Symposium on Circuits and Systems (ISCAS), October 2020. [link]
  15. U. Banerjee, T. S. Ukyab, A. P. Chandrakasan, “A Low-Power Side-Channel-Secure Configurable Accelerator for Post-Quantum Lattice-Based Cryptography,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) Design Contest, August 2020. [link]
  16. S. Maji, U. Banerjee, S. H. Fuller, M. R. Abdelhamid, P. M. Nadeau, R. T. Yazicigil, A. P. Chandrakasan, “A Low-Power Dual-Factor Authentication Unit for Security of Implantable Devices,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) Design Contest, August 2020. [link]
  17. U. Banerjee, A. P. Chandrakasan, “Efficient Post-Quantum TLS Handshakes using Identity-Based Key Exchange from Lattices,” IEEE International Conference on Communications (ICC), June 2020. [link]
  18. S. Maji, U. Banerjee, S. H. Fuller, M. R. Abdelhamid, P. M. Nadeau, R. T. Yazicigil, A. P. Chandrakasan, “A Low-Power Dual-Factor Authentication Unit for Secure Implantable Devices,” IEEE Custom Integrated Circuits Conference (CICC), March 2020. [link]
  19. U. Banerjee, T. S. Ukyab, A. P. Chandrakasan, “Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols,” IACR Conference on Cryptographic Hardware and Embedded Systems (CHES), August 2019. [link]
  20. U. Banerjee, A. Pathak, A. P. Chandrakasan, “An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things,” IEEE International Solid-State Circuits Conference (ISSCC), February 2019. [link]
  21. U. Banerjee, C. Juvekar, A. Wright, Arvind, A. P. Chandrakasan, “An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for End-to-End Security in IoT Applications,” IEEE International Solid-State Circuits Conference (ISSCC), February 2018. [link]
  22. U. Banerjee, C. Juvekar, S. H. Fuller, A. P. Chandrakasan, “eeDTLS: Energy-Efficient Datagram Transport Layer Security for the Internet of Things,” IEEE Global Communications Conference (GLOBECOM), December 2017. [link]