E0 217: Efficient and Secure Digital Circuits and Systems (August 2025)

 

Instructor: Utsav Banerjee

Lecture Timings: Monday & Wednesday 11am-12pm

Lab / Tutorial Timings: Thursday 5:30pm

Location: Ground Floor Classroom (DESE 137)

Teaching Assistants: Alamuru Pavan Kumar Reddy, Shubham Lanjewar, Sudipta Debnath, Kiran Magar, Rishabh Shrivastava

 

Course Description: This is an introductory graduate-level course on the design and analysis of digital circuits and systems with an emphasis on efficient and secure implementation aspects. This course will cover co-optimization of circuits, architectures and algorithms for the design of application-specific digital systems with different power, performance, area and energy-efficiency requirements. Techniques for securing such systems using efficient implementation of encryption, authentication and side-channel countermeasures will also be covered. Various digital circuit and system concepts will be introduced using a combination of lectures, homework assignments and a project.

Prerequisites: Basic understanding of digital electronic circuits.

Credits: 2:1

Syllabus:
▶ Circuits: overview of CMOS digital circuit design, logic gates, combinational and sequential logic, finite state machines, arithmetic circuits, memories, timing considerations, power consumption
▶ Systems: overview of computer architecture, instruction set, hardware-software interaction, micro-controllers, hardware acceleration, FPGA and ASIC design
▶ Efficiency: gate-level optimization for power-performance-area, low-power versus energy-efficient implementation, pipelining, multi-level memories and caches
▶ Security: introduction to cryptography and hardware security, implementation of multi-precision modular arithmetic, side-channel attacks and countermeasures

References:
1. J. M. Rabaey, A. P. Chandrakasan and B. Nikolic, “Digital Integrated Circuits: A Design Perspective”.
2. N. H. E. Weste and D. M. Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”.
3. D. M. Harris and S. L. Harris, “Digital Design and Computer Architecture”.
4. M. M. Mano and M. D. Ciletti, “Digital Design”.
5. Journal / Magazine Articles and Conference Papers.

 

Grading: The grade will be based on five problem sets, two mid term exams, a final exam and a project. Assignments must be submitted by 11:59pm on the day they are due. Late submissions will not be accepted for grading. The final grade will be calculated approximately based on the following weights: Problem Sets (10%), Mid Term Exam 1 (10%), Mid Term Exam 2 (15%), Project (20%) and Final Exam (45%).

Problem Sets: The problem sets will contain questions based on numerical calculations as well as circuit / system / software simulations. Various open-source tools will be used for the simulation tasks and their setup instructions will be shared during the lab tutorials.

Project: There will be a set of well-defined projects to choose from and conduct in groups of 2. These projects will provide hands-on experience with the analysis and implementation aspects of digital circuits and systems. The recommended projects for this term involve the design, simulation and implementation of one of the following:
1. Floating Point Multiplier
2. Transcendental Function Accelerator
3. Fast Fourier Transform Accelerator
4. Perceptron Accelerator
5. Light Weight Cryptography Accelerator
6. Large Integer Modular Multiplier
7. Mini RISC Processor

Course Materials: Lecture slides, tutorials, simulation models, projects and additional readings will be shared using a Microsoft Teams group which will be accessible only to registered students.

 

Schedule:

		Reference Textbook Chapter Readings
Lecture	Topic	Ref. 1	Ref. 2	Ref. 3	Ref. 4
1	Introduction and Course Overview	1, 2	1
2	MOS Transistor	3	2
3	CMOS Inverter (Part 1)	5	2
4	CMOS Inverter (Part 2)	5	2
5	Combinational and Sequential Logic	6, 7	9, 10	1 – 3	1 – 6
6	Timing and Power Considerations	6, 7, 10	4, 5, 9, 10
7	Arithmetic Circuits (Part 1)	11	11	5
8	Arithmetic Circuits (Part 2)	11	11	5
9	Memories	12	12	5	7
10	Design Trade-Offs (Part 1)
11	Design Trade-Offs (Part 2)
12	Processor Architecture (Part 1)			6, 7
13	Processor Architecture (Part 2)			6, 7
14	Processor Architecture (Part 3)			6, 7
15	Processor Architecture (Part 4)			6, 7
16	FPGA and ASIC	8	14
17	Hardware Accelerators
18	Hardware Acceleration for DSP & AI / ML
19	Cryptography and Hardware Security
20	Hardware Acceleration for Cryptography
21	Hardware Security Primitives
22	Side-Channel Analysis
23	Advanced Topics