The past decade has witnessed a remarkable evolution in the field of electronics in terms of miniaturization of devices, reduction of total power consumption, portability of the systems, etc. Nevertheless, the Moore’s scaling law is approaching its physical limits rapidly, for the existing Si-based technology. As the device dimensions keep on reducing, short channel effects like Drain induced barrier lowering (DIBL) and VT roll-off are becoming more and more prominent. After exploring graphene, researchers have gained lot of interests in two dimensional (2D) layered materials like single layer transition metal dichalcogenides (TMDs), hBN, etc. Among those, the TMDs seem to be the good fix for MOSFET scaling issues. They offer good electrostatic control than their bulk counterparts. Moreover, they are covalently bonded solid, where the adjacent stacking layers are held by weak van der Waals force. Hence, they can easily be exfoliated into monolayers, which are free from dangling bonds as well. Among the various TMDs, MoS2 (Molybednum Disulfide), seems to be ideal candidate for research, due to its direct bandgap of 1.8 eV, high on to off current ratio and reasonably good carrier mobility. However, realization of low resistance contacts at source/drain terminals of MoS2 transistor is a very big challenge. This attributes to the low on-current in MoS2. Experimental techniques where local metallic phase is deposited on usual semiconducting MoS2 have attracted lot of attention. In conjunction with the experiments, density functional theory (DFT) based atomistic modeling of metal-2D material interface is important to get insights on the charge transfer through these systems. Therefore in this work, we have used DFT to compare the Schottky barrier height (SBH) of two polytypes of phase engineered MoS2 by calculating their elecronic structures. We also propose a novel asymmetric Au-MoS2-Au atomistic model to assess the carrier transport, estimate the contact resistance values of hetero interface using Non Equilibrium Green’s Function(NEGF) approach. We have shown that the contact resistance of Au-1T0-Au has decreased by three-fold compared to Au-2H-Au device.

Researcher : Richa Chakravarty, ME Micro (2016).

Multi-gate (double-gate, tri-gate or quad-gate) MOSFETs are necessary to replace the conventional bulk MOSFET for CMOS scaling to proceed unhindered in the future. Among the class of double-gate devices, the independent double gate (IDG) MOSFET offers maximum design exibility owing to the independent control of the two gate terminals with the ability to dynamically modulate the threshold voltage and the transconductance. Hence, the development of surface potential based compact models to accurately characterize the IDG MOSFET behavior has received considerable attention in recent times. This work aims to address some potential problems in this area. Surface potential based compact models require a fast and accurate solution of the input voltage equations (referred to as the P-IVEs or Primary IVEs) derived from the Poisson equation, to determine the surface potential values at the source and drain ends and hence compute the other physical parameters of the transistor. For the IDG MOSFET, a robust numerical solution of the implicit P-IVEs requires the use of Root bracketing methods (RBMs) instead of the commonly used Newton-Raphson (NR) technique due to the presence of non-removable discontinuity and singularity in the P-IVEs. In this work, an exhaustive study of the different RBMs available in the literature is conducted and a single, derivative-free RBM (LZ4) offering faster convergence than the earlier proposed hybrid NR-Ridders algorithm is proposed to solve both the trigonometric and hyperbolic P-IVEs of the IDG MOSFET. With some adjustments to the solution space for the trigonometric P-IVE, a further reduction of the computation time is achieved. The improvement of computational efficiency is demonstrated to be about 60% for trigonometric P-IVE and about 15% for hyperbolic P-IVE after implementation in a commercial circuit simulator through the Verilog-A interface and simulation of a variety of circuit blocks. Accurate modeling of terminal charges forms an important part of compact models. To overcome the limitations of the traditional charge linearization techniques for IDG MOSFET, a piecewise linearization technique for calculating the terminal charges is necessary. This requires formulating an additional set of IVEs, referred to as the S-IVEs or Secondary IVEs. The S-IVEs help to determine the surface potential at some pre- determined points along the channel. The nature of the Secondary IVEs is investigated here and an efficient solution methodology is proposed. The proposed solution is also implemented in a circuit simulator to compare the solution time with that for the P-IVEs. Although sufficiently accurate in predicting the device behavior in strong inversion, compact models for the IDG MOSFET based on the unipolar Poisson equation solution have a few limitations. These include the inability to accurately model the accumulation and near at band regions of operation. Varactor modeling of the IDG MOSFET also demands a complete solution of the bipolar Poisson equation. Here, we rigourously solve the Bipolar Poisson equation to derive an analytical model involving the Legendre’s incomplete elliptic integral of the rst kind and Jacobian elliptic functions. The proposed model is constructed along similar lines as that for the unipolar Poisson equation solution and it is seen that the device behavior is again governed by different sets of IVEs based on the bias condition. After investigating the solution space for the set of IVEs obtained, we employ the LZ4 RBM to solve the IVEs and obtain the potential profle for various bias conditions. The results thus obtained show good agreement with the numerical solution of the Poisson equation under all bias conditions.

Researcher : Abraham Aby, ME Micro (2012).

Single-Walled Carbon Nanotube (SWCNT) based Very Large Scale Integrated circuit (VLSI) interconnect is one of the emerging technologies, and has the potential to over- come the thermal issues persisting even with the advanced copper based interconnect. This is because of it’s promising electrical and thermal transport properties. It can be stated that thermal energy transport in SWCNTs is highly anisotropic due to the quasi one dimensionality, and like in other allotropes of carbon, phonons are the dominant energy carriers of heat conduction. In case of conventional interconnect materials, cop- per and aluminium, although their thermal conductivity varies over orders of magnitude at temperatures below 100 K, near room temperature and above they have almost con- stant value. On the other hand, the reported experimental studies on suspended metallic SWCNTs illustrate a wide variation of the longitudinal lattice thermal conductivity (κ l ) with respect to the temperature (T) and the tube length (L) at low, room and high temperatures. Physics based analytical formulation of κ l of metallic SWCNT as a func- tion of L and T is essential to efficiently quantify this emerging technology’s impact on the rising thermal management issues of Integrated Circuits. In this work, a physics based diameter independent analytical model for κ l of metal- lic SWCNT is addressed as a function of L over a wide range of T. Heat conduction in metallic SWCNTs is governed by three resistive phonon scattering processes; second order three phonon Umklapp scattering, mass difference scattering and boundary scat- tering. For this study, all the above processes are considered, and the effective mode dependent relaxation time is determined by the Matthiessen’s rule. Phonon Boltzmann transport equation under the single mode relaxation time approximation is employed toderive the non-equilibrium distribution function. The heat flux as a function of temper- ature gradient is obtained from this non-equilibrium distribution function. Based on the Fourier’s definition of thermal conductivity, κ l of metallic SWCNT is formulated and the Debye approximations are used to arrive at an analytical model. The model developed is validated against both the low and high temperature exper- imental investigations. At low temperatures, thermal resistance of metallic SWCNT is due to phonon-boundary scattering process, while at high temperatures it is governed by three phonon Umklapp scattering process. It is understood that apart from form factor due to mass difference scattering, boundary scattering also plays the key role in determining the peak value. At room temperature, κ l of metallic SWCNT is found to be an order of magnitude higher than that of most of metals. The reason can be attributed to the fact that both sound velocity and Debye temperature which have direct effect on the phonon transport in a solid, are reasonably higher in SWCNTs. Though Umklapp processes reduce the κ l steeper than 1/T beyond room-temperature, it’s magnitude is around 1000 W/m/K upto 800 K for various tube lengths, which confirms that this novel material is indeed an efficient conductor of heat also, at room-temperature and above.

Researcher : A.Rex, M.Sc. Engineering (2011).

The quasi-static approximation assumes that the charge density at any position in the channel changes instantaneously with the applied voltages i.e., it assumes the transit time in the channel to be zero. More specifically, if QI = f(VD, VS, VG) (capitalized subscripts refer to DC quantities), Qi = f(Vd, Vs, Vg) where small subscripts refer to time varying quantities. However since the channel transit time is not zero, analyses based on the quasi-static approximation introduce errors for rapidly changing terminal voltages due to the distributed nature of the MOSFET. At high frequencies, the transit time L vd becomes comparable to the time period of the terminal ac voltages, so there is a finite time lag between the voltage and the response of the channel charge to the voltage. Models that take into account the distributed nature of the transistor are described as nonquasi- static (NQS) models. The derivation of NQS models is not a simple task since it requires the solution of both transport and continuity equations. The aim of this work is to predict the behaviour of Symmetric Double Gate (SDG) and Gate-All-Around (GAA)MOSFET under high frequency small signal variations as well as large signal fast transients. In case of small signal analysis, the time variations can be replaced by j!n and consequently, the problem reduces to solving an ordinary differential equation. High frequency analyses are mostly done in terms of admittance (y) parameters, consequently the objective of small signal analysis is to observe the variation of y parameters of the device as a function of frequency. For large signal analysis, we have to solve a non linear parabolic partial differential equation. Here the main objective is to derive equations that can accurately predict the terminal currents when an input voltage of rise time sufficiently less than the transit time is applied. The large signal analysis is extremely rigorous and no complete analytical solution exists till date.

Researcher : Sudipta Sarkar, M.E. Micro (2010).

FinFET has appeared as the most promising device architecture to realize Multiple Gate MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) on Silicon wafers due to its self-aligned process steps and compatibility with conventional planar CMOS (Complementary Metal Oxide Semiconductor) technology. A generic FinFET architecture is a triple gate (TG) MOSFET in nature and can be converted into double gate or quadruple gate MOSFET by scaling the oxide thicknesses appropriately. Though several analytical models have been proposed for symmetric double gate MOSFETs and a few for asymmetric/independent double gate MOSFETs, no physical model has been reported for triple gate transistors. This is due to complexity in solving the 2D Poisson’s equation which has exponential nonlinearity on its right hand side. In this work effort has been put to derive analytical model for the inversion charge of TG FinFET, which is the fundamental step for developing a compact model. From the governing two-dimensional Poisson’s equation, it is rigorously shown that the total inversion charge in a TG FinFET can be partitioned into three components: charge originating from constituent symmetric double gate (SDG), constituent independent double gate (IDG), and a coupling component. It is shown that the analytical expression for the inversion charge originating from SDG and IDG components can be formulated from existing models, however it is very difficult to obtain a simplified analytical expression for the coupling term. Based on few practical approximations, we propose some techniques for modeling the coupling term. Models obtained using these techniques are validated against numerical simulation in all operation regimes for a wide range of device parameters. In this development we have neglected the corner effect as it is insignificant in undoped body devices. While deriving the inversion charge model for FinFET, it is observed that previous techniques [Lu and Taur, IEEE Trans. Elec. Dev., Vol. 53,No. 5, 2006, Conde et al., IEEE Trans. Elec. Dev., Vol. 54, No. 1, 2007 and Liu et al., IEEE Trans. Elec. Dev., Vol. 55, No.3, 2008] used for solving the one-dimensional Poisson’s equation rigorously for long channel asymmetric and independent double gate transistor result in potential model that involves multiple inter-coupled implicit equations. As these equations need to be solved self-consistently, such potential models are clearly inefficient for compact modeling. This work also reports a different rigorous technique for solving the same Poisson equation by which one can obtain the potential profile of a generalized independent double gate transistor that involves a single implicit equation. Proposed model appears to be much more computationaly efficient for circuit simulation than the previous models.

Researcher : Avinash Saho, M.Sc. Engineering (2009).

Silicon nanowire based multiple gate metal oxide field effect transistors (MG-MOSFET) appear as replacements for conventional bulk transistors in post 45nm technology nodes. In such transistors the short channel effect (SCE) is controlled by the device geometry, and hence an undoped (or, lightly doped) ultra-thin body silicon nanowire is used to sustain the channel. The use of undoped body also solves several issues in bulk MOSFETs e.g., random dopant fluctuations, mobility degradation and compatibility with midgap metal gates. The electrostatic integrity of such devices increases with the scaling down of the body thickness. Since the quantization of electron energy cannot be ignored in such ultra-thin body devices, it is extremely important to consider quantum effects in their threshold voltage models. Most of the models reported so far are valid for long channel double gate devices. Only Muntenu et al. [Journal of non-crystalline solids vol 351 pp 1911-1918 2005] have reported threshold voltage model for short channel symmetric double gate MOSFET, however it involves unphysical fitting parameters. On the other hand no compact modeling work has been reported for other types of MG-MOSFETs (e.g., tri gate, quad gate, cylindrical body) apart from numerical simulation results. In this work we report physically based closed form quantum threshold voltage models for short channel symmetric double gate, quad gate and cylindrical body gate-all-around MOSFETs. In these devices quantum effects aries mainly due to the structural confinement of electron energy. Proposed models are based on the analytical solution of two or three-dimensional Poisson equation and one or two-dimensional Schroedinger equation depending on the device geometries. Judicial approximations have been taken to simplify the models in order to make them closed form and efficient for large scale circuit simulation. Effort has also been put to model the quantum threshold voltage of tri gate MOSFET. However it is found that the energy quantization in tri gate devices are mainly due to electronic confinement and hence it is very difficult to develop closed form analytical equations for the threshold voltage. Thus in this work the modeling of tri gate devices have been limited to long channel cases. All the models are validated againt the professional numerical simulator.

Researcher : P. Rakesh Kumar, M.Sc. Engineering (2009).

Undoped body multi gate (MG) Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are appearing as replacements for single gate bulk MOSFET in forthcoming sub-45nm technology nodes. It is therefore extremely necessary to develop compact models for MG transistors in order to use them in nano-scale integrated circuit design and simulation. There is however a sharp distinction between the electrostatics of traditional bulk transistors and undoped body devices. In bulk transistor, where the substrate is sufficiently doped, the inversion charges are located close to the surface and hence the surface potential solely controls the electrostatic integrity of the device. However, in undoped body devices, gate electric field penetrates the body center, and inversion charge exists throughout the body. In contrast to the bulk transistors, depending on device geometry, the potential of the body center of undoped body devices could be higher than the surface in weak inversion regime and the current ows through the center-part of the device instead of surface. Several crucial parameters (e.g. Sub-threshold slope) sometimes become more dependable on the potential of body center rather than the surface. Hence the body-center potential should also be modeled correctly along with the surface-potential for accurate calculation of inversion charge, threshold voltage and other related parameters of undoped body multi-gate transistors. Although several potential models for MG transistors have been proposed to capture the short channel behavior in the subthreshold regime but most of them are based on the crucial approximation of coverting the 2D Poisson’s equation into Laplace equation. This approximation holds good only at surface but breaks down at body center and in the moderate inversion regime. As a result all the previous models fail to capture the potential of body center correctly and remain valid only in weak-inversion regime. In this work we have developed semiclassical compact models for potential distribution for double gate (DG) and cylindrical Gate-All-Around (GAA) transistors. The models are based on the analytical solution of 2D Poisson’s equation in the channel region and valid for both: a) weak and strong inversion regimes, b) long channel and short channel transistors, and, c) body surface and center. Using the proposed model, for the first time, it is demonstrated that the body potential versus gate voltage characteristics for the devices having equal channel lengths but different body thicknesses pass through a single common point (termed as crossover point). Using the concept of “crossover point” the effect of body thickness on the threshold voltage of undoped body multi-gate transistors is explained. Based on the proposed body potential model, a new compact model for the subthreshold swing is formulated. Some other parameters e.g. inversion charge, threshold voltage roll-off etc are also studied to demonstrate the impact of body center potential on the electrostatics of multi gate transistor. All the models are validated against professional numerical device simulator.

Researcher : Biswajit Ray, M.Sc. Enginering (2008).

Interconnects constitute a dominant source of circuit delay for modern chip de- signs. As scaling of technology continues chip interconnects are also been shrinking down. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this thesis, a practical interconnect delay variational analysis technique is presented to facilitate efficient evaluation of wire performance variability. we model the interconnect process variability by converting the telegrapher equation with random coefficients into stochastic differential equation. We measured how accurately this conversion works to map process variations into the variability of the output delay. Later, we propose a novel and efficient algorithm for modeling interconnect- networks in the presence of process variation. We develop a method for delay analysis of interconnects considering the impact of Gaussian metal process variations. The resistance and capacitance of a distributed RC line are expressed as independent Gaussian random variables which are then used to compute the standard deviation of delay Probability Distribution Functions at all nodes in the interconnect network. We validate the accuracy of our approach against SPICE based Monte Carlo simulations while having greatly lowered the computational cost.

Researcher : Sivakumar Bondada, M.E. Micro (2008).

The Tunnel Field Effect Transistor (TFET) with sub-60mV/decade Sub-threshold slope and extremely high ION/IOFF ratio has attracted enough attention for low standby power (LSTP) applications where the battery life is very important. So far research in this area has been limited to numerical simulation and experimental analysis. It is however extremely necessary to develop compact models for TFET in order to use them in nano-scale integrated circuit design and simulation. In this work, for the first time, we develop analytical Sub-threshold slope model for n-channel double gate TFET (nDGTFET). Unlike conventional FETs, current in TFET is mainly controlled by the band-to-band tunneling mechanism at source/channel interface. As the total drain cur- rent is proportional to band-to-band generation rate, the main challenge in the present work is to find an explicit relationship between average electric field over the tunneling path and the applied gate voltage under nonlocal tunneling condition. Two dimensional Poisson’s equation (with Laplace approximation) is first solved in a rectangular coordi- nate system in order to obtain analytical expression for electron energy distribution over the channel region. Kane’s Model [J. Phy. Chem. Solids 12(181) 1959] for band-to-band tunneling along with some analytical approximation techniques are then used to derive the expression for the Sub-threshold slope under nonlocal tunneling conditions. This Sub-threshold slope model is verified against professional numerical device simulator (MEDICI) for different device geometries. Being an asymmetric device, TFET fabrication suffers from source misalignment with gate. As the doping in source and drain-gate are different, conventional-FET- like self-aligned gate stack formation is not possible for TFET. Such misalignment, at source side, seriously degrades the performance of TFETs. To overcome this problem, in this work we explore the possibility of using “gate replacement” technique for TFET fabrication. We first develop process flow for single gate bulk nTFET, and then we extend it to n-channel double gate TFET (nDGTFET) using modified FinFET process. Good alignments between source and gate are observed with TCAD-simulations in both the cases.

Researcher : Ramesha A, M.Sc. Engineering (2008).

Continuous downscaling of CMOS technology has led to immense improvements in its performance. However, the switching characteristics of the present day MOSFET switch are far from the ideal one. For the Ideal switch the sub-threshold swing is zero and this leads to zero off-state current. This off-state current is the most crucial parameter for the low standby power applications (e.g. cellular phone) as it determines the battery life of the device. The minimum value of the sub-threshold swing of today’s MOSFET is physically limited to 60mV/decade at room temperature due to the drift-diffusion mode of carrier transport. In fact in ultra-short channel MOSFET the sub-threshold swing is further deteriorated due to several parasitic effects (e.g., punch through, short channel effects etc). Therefore for future low standby power application one requires alternative MOSFET architecture which uses different type of carrier transport mechanism. The aim of this thesis is to explore the various available options and to come up with a technology which is CMOS compatible and solves the problem of increased leakage for low standby power applications. The Tunnel Field Effect Transistor (TFET) with perfect saturation in the output characteristics, sub-60mV/decade subthreshold swing and extremely high ION/IOFF ratio has attracted a lot of attention for such applications. However, due to extremely low IOFF , even though it has a very good ION/IOFF ratio, it fails to meet the technology requirements of ION. To overcome this problem of low ION, in this work, we have proposed a new Tunnel FET architecture with SiGe layer at the source end. The improvement in ION is achieved by modulating the bandgap at the tunneling junction by varying the Ge mole fraction in the SiGe layer. By the use of 2D device simulation, we demonstrate that the proposed device is scalable upto channel lengths as small as 30 nm. Also, the device becomes nearly free from DIBL as the germanium mole fraction is increased. A CMOS compatible process flow to fabricate the proposed device is discussed. The compatibility of the process flow with the standard CMOS process makes the proposed device highly attractive for future low stand-by power applications.

Researcher : Nayan Bhogilal Patel, M.Sc. Engineering (2007).

As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits, many novel device structures are being extensively explored. Among them, the Silicon Nanowire Field Effect Transistor (Si- NWFET) has attracted broad attention from both the semiconductor industry and academia. Currently, there is intense interest in one dimensional silicon nanowires due to their excellent transport properties, compact size and compatibility with silicon technology. In nanoscale regime, it has become extremely important and essential to have quantum mechanical approach based simulation techniques to understand the working and performance limits of Si-NWFET. One such approach is Non-Equilibrium Green’s Function (NEGF) formalism. NEGF approach provides a rigorous description of quantum transport and scattering effects. In this work, the electrostatics and carrier dynamics of Si-NWFET, the most promising device structure in nanoscale regime have been studied. The scaling of a few key device parameters have been carried out to observe the variations in the properties of Si-NWFET in nanoscale regime. The quantum mechanical effects on electrostatics and carrier transport in Si-NWFETs have been simulated and studied using quantum mechanical simulators (provided by nanohub.org ). The comparison has been made between the simulation results obtained from professional device simulator (Sentaurus Device), which uses the semiclassical transport analysis and quantum mechanical simulator for multigate ultra thin body devices(Double gate-MOSFET and Si-NWFET) and observed the essential of quatum mechanical simulation in nanoscale regime. The Si-NWFET with rectangular and circular channel were simulated to compare the device characteristics. Finally, the performance of Si-NWFET is compared with Double gate-MOSFET.

Researcher : Shubhakar,M.E. Micro (2007).

Single electronics has attracted a lot of attention as an emerging nanotechnology due to its ultra low power dissipation, new functionalities, nano feature size and CMOS compatible fabrication process. It is imperative to explore the feasibility of using any new technology to build logic gates. In this thesis, a compact model for noise margins (NM) of SET Logic is developed which is a function of device capacitances and background charge (ζ). Noise margin is then used as a metric to evaluate the robustness of SET logic against ζ, temperature, variation of SET parameters (CT and CG), and energy quantization of the dot. It is shown that choosing ζ = CT=CG = 1/3, maximizes NM . An estimate of the maximum tolerable ζ, can be obtained and is shown to be equal to ±0:03e. The effect of energy quantization is studied through simulations and is found to degrade SET Logic performance. Finally the effect of mismatch in device parameters (CT and CG) on NM is studied through exhaustive simulations, which indicate that α Є [0.3, 0.4] for maximum robustness. It is also observed that mismatch can have a huge impact on static power.

Researcher : Chaitanya Sathe, M.E. Micro (2007).

 The past decade has witnessed a remarkable evolution in the field of electronics in terms of miniaturization of devices, reduction of total power consumption, portability of the systems, etc. Nevertheless, the Moore’s scaling law is approaching its physical limits rapidly, for the existing Si-based technology. As the device dimensions keep on reducing, short channel effects like Drain induced barrier lowering (DIBL) and VT roll-off are becoming more and more prominent. After exploring graphene, researchers have gained lot of interests in two dimensional (2D) layered materials like single layer transition metal dichalcogenides (TMDs), hBN, etc. Among those, the TMDs seem to be the good fix for MOSFET scaling issues. They offer good electrostatic control than their bulk counterparts. Moreover, they are covalently bonded solid, where the adjacent stacking layers are held by weak van der Waals force. Hence, they can easily be exfoliated into monolayers, which are free from dangling bonds as well. Among the various TMDs, MoS2 (Molybednum Disulfide), seems to be ideal candidate for research, due to its direct bandgap of 1.8 eV, high on to off current ratio and reasonably good carrier mobility. However, realization of low resistance contacts at source/drain terminals of MoS2 transistor is a very big challenge. This attributes to the low on-current in MoS2. Experimental techniques where local metallic phase is deposited on usual semiconducting MoS2 have attracted lot of attention. In conjunction with the experiments, density functional theory (DFT) based atomistic modeling of metal-2D material interface is important to get insights on the charge transfer through these systems. Therefore in this work, we have used DFT to compare the Schottky barrier height (SBH) of two polytypes of phase engineered MoS2 by calculating their elecronic structures. We also propose a novel asymmetric Au-MoS2-Au atomistic model to assess the carrier transport, estimate the contact resistance values of hetero interface using Non Equilibrium Green’s Function(NEGF) approach. We have shown that the contact resistance of Au-1T0-Au has decreased by three-fold compared to Au-2H-Au device.

Researcher : Richa Chakravarty, ME Micro (2016).

Multi-gate (double-gate, tri-gate or quad-gate) MOSFETs are necessary to replace the conventional bulk MOSFET for CMOS scaling to proceed unhindered in the future. Among the class of double-gate devices, the independent double gate (IDG) MOSFET offers maximum design exibility owing to the independent control of the two gate terminals with the ability to dynamically modulate the threshold voltage and the transconductance. Hence, the development of surface potential based compact models to accurately characterize the IDG MOSFET behavior has received considerable attention in recent times. This work aims to address some potential problems in this area. Surface potential based compact models require a fast and accurate solution of the input voltage equations (referred to as the P-IVEs or Primary IVEs) derived from the Poisson equation, to determine the surface potential values at the source and drain ends and hence compute the other physical parameters of the transistor. For the IDG MOSFET, a robust numerical solution of the implicit P-IVEs requires the use of Root bracketing methods (RBMs) instead of the commonly used Newton-Raphson (NR) technique due to the presence of non-removable discontinuity and singularity in the P-IVEs. In this work, an exhaustive study of the different RBMs available in the literature is conducted and a single, derivative-free RBM (LZ4) offering faster convergence than the earlier proposed hybrid NR-Ridders algorithm is proposed to solve both the trigonometric and hyperbolic P-IVEs of the IDG MOSFET. With some adjustments to the solution space for the trigonometric P-IVE, a further reduction of the computation time is achieved. The improvement of computational efficiency is demonstrated to be about 60% for trigonometric P-IVE and about 15% for hyperbolic P-IVE after implementation in a commercial circuit simulator through the Verilog-A interface and simulation of a variety of circuit blocks. Accurate modeling of terminal charges forms an important part of compact models. To overcome the limitations of the traditional charge linearization techniques for IDG MOSFET, a piecewise linearization technique for calculating the terminal charges is necessary. This requires formulating an additional set of IVEs, referred to as the S-IVEs or Secondary IVEs. The S-IVEs help to determine the surface potential at some pre- determined points along the channel. The nature of the Secondary IVEs is investigated here and an efficient solution methodology is proposed. The proposed solution is also implemented in a circuit simulator to compare the solution time with that for the P-IVEs. Although sufficiently accurate in predicting the device behavior in strong inversion, compact models for the IDG MOSFET based on the unipolar Poisson equation solution have a few limitations. These include the inability to accurately model the accumulation and near at band regions of operation. Varactor modeling of the IDG MOSFET also demands a complete solution of the bipolar Poisson equation. Here, we rigourously solve the Bipolar Poisson equation to derive an analytical model involving the Legendre’s incomplete elliptic integral of the rst kind and Jacobian elliptic functions. The proposed model is constructed along similar lines as that for the unipolar Poisson equation solution and it is seen that the device behavior is again governed by different sets of IVEs based on the bias condition. After investigating the solution space for the set of IVEs obtained, we employ the LZ4 RBM to solve the IVEs and obtain the potential profle for various bias conditions. The results thus obtained show good agreement with the numerical solution of the Poisson equation under all bias conditions.

Researcher : Abraham Aby, ME Micro (2012).

The quasi-static approximation assumes that the charge density at any position in the channel changes instantaneously with the applied voltages i.e., it assumes the transit time in the channel to be zero. More specifically, if QI = f(VD, VS, VG) (capitalized subscripts refer to DC quantities), Qi = f(Vd, Vs, Vg) where small subscripts refer to time varying quantities. However since the channel transit time is not zero, analyses based on the quasi-static approximation introduce errors for rapidly changing terminal voltages due to the distributed nature of the MOSFET. At high frequencies, the transit time L vd becomes comparable to the time period of the terminal ac voltages, so there is a finite time lag between the voltage and the response of the channel charge to the voltage. Models that take into account the distributed nature of the transistor are described as nonquasi- static (NQS) models. The derivation of NQS models is not a simple task since it requires the solution of both transport and continuity equations. The aim of this work is to predict the behaviour of Symmetric Double Gate (SDG) and Gate-All-Around (GAA)MOSFET under high frequency small signal variations as well as large signal fast transients. In case of small signal analysis, the time variations can be replaced by j!n and consequently, the problem reduces to solving an ordinary differential equation. High frequency analyses are mostly done in terms of admittance (y) parameters, consequently the objective of small signal analysis is to observe the variation of y parameters of the device as a function of frequency. For large signal analysis, we have to solve a non linear parabolic partial differential equation. Here the main objective is to derive equations that can accurately predict the terminal currents when an input voltage of rise time sufficiently less than the transit time is applied. The large signal analysis is extremely rigorous and no complete analytical solution exists till date.

Researcher : Sudipta Sarkar, M.E. Micro (2010).

FinFET has appeared as the most promising device architecture to realize Multiple Gate MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) on Silicon wafers due to its self-aligned process steps and compatibility with conventional planar CMOS (Complementary Metal Oxide Semiconductor) technology. A generic FinFET architecture is a triple gate (TG) MOSFET in nature and can be converted into double gate or quadruple gate MOSFET by scaling the oxide thicknesses appropriately. Though several analytical models have been proposed for symmetric double gate MOSFETs and a few for asymmetric/independent double gate MOSFETs, no physical model has been reported for triple gate transistors. This is due to complexity in solving the 2D Poisson’s equation which has exponential nonlinearity on its right hand side. In this work effort has been put to derive analytical model for the inversion charge of TG FinFET, which is the fundamental step for developing a compact model. From the governing two-dimensional Poisson’s equation, it is rigorously shown that the total inversion charge in a TG FinFET can be partitioned into three components: charge originating from constituent symmetric double gate (SDG), constituent independent double gate (IDG), and a coupling component. It is shown that the analytical expression for the inversion charge originating from SDG and IDG components can be formulated from existing models, however it is very difficult to obtain a simplified analytical expression for the coupling term. Based on few practical approximations, we propose some techniques for modeling the coupling term. Models obtained using these techniques are validated against numerical simulation in all operation regimes for a wide range of device parameters. In this development we have neglected the corner effect as it is insignificant in undoped body devices. While deriving the inversion charge model for FinFET, it is observed that previous techniques [Lu and Taur, IEEE Trans. Elec. Dev., Vol. 53,No. 5, 2006, Conde et al., IEEE Trans. Elec. Dev., Vol. 54, No. 1, 2007 and Liu et al., IEEE Trans. Elec. Dev., Vol. 55, No.3, 2008] used for solving the one-dimensional Poisson’s equation rigorously for long channel asymmetric and independent double gate transistor result in potential model that involves multiple inter-coupled implicit equations. As these equations need to be solved self-consistently, such potential models are clearly inefficient for compact modeling. This work also reports a different rigorous technique for solving the same Poisson equation by which one can obtain the potential profile of a generalized independent double gate transistor that involves a single implicit equation. Proposed model appears to be much more computationaly efficient for circuit simulation than the previous models.

Researcher : Avinash Saho, M.Sc. Engineering (2009).

Silicon nanowire based multiple gate metal oxide field effect transistors (MG-MOSFET) appear as replacements for conventional bulk transistors in post 45nm technology nodes. In such transistors the short channel effect (SCE) is controlled by the device geometry, and hence an undoped (or, lightly doped) ultra-thin body silicon nanowire is used to sustain the channel. The use of undoped body also solves several issues in bulk MOSFETs e.g., random dopant fluctuations, mobility degradation and compatibility with midgap metal gates. The electrostatic integrity of such devices increases with the scaling down of the body thickness. Since the quantization of electron energy cannot be ignored in such ultra-thin body devices, it is extremely important to consider quantum effects in their threshold voltage models. Most of the models reported so far are valid for long channel double gate devices. Only Muntenu et al. [Journal of non-crystalline solids vol 351 pp 1911-1918 2005] have reported threshold voltage model for short channel symmetric double gate MOSFET, however it involves unphysical fitting parameters. On the other hand no compact modeling work has been reported for other types of MG-MOSFETs (e.g., tri gate, quad gate, cylindrical body) apart from numerical simulation results. In this work we report physically based closed form quantum threshold voltage models for short channel symmetric double gate, quad gate and cylindrical body gate-all-around MOSFETs. In these devices quantum effects aries mainly due to the structural confinement of electron energy. Proposed models are based on the analytical solution of two or three-dimensional Poisson equation and one or two-dimensional Schroedinger equation depending on the device geometries. Judicial approximations have been taken to simplify the models in order to make them closed form and efficient for large scale circuit simulation. Effort has also been put to model the quantum threshold voltage of tri gate MOSFET. However it is found that the energy quantization in tri gate devices are mainly due to electronic confinement and hence it is very difficult to develop closed form analytical equations for the threshold voltage. Thus in this work the modeling of tri gate devices have been limited to long channel cases. All the models are validated againt the professional numerical simulator.

Researcher : P. Rakesh Kumar, M.Sc. Engineering (2009).

Undoped body multi gate (MG) Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are appearing as replacements for single gate bulk MOSFET in forthcoming sub-45nm technology nodes. It is therefore extremely necessary to develop compact models for MG transistors in order to use them in nano-scale integrated circuit design and simulation. There is however a sharp distinction between the electrostatics of traditional bulk transistors and undoped body devices. In bulk transistor, where the substrate is sufficiently doped, the inversion charges are located close to the surface and hence the surface potential solely controls the electrostatic integrity of the device. However, in undoped body devices, gate electric field penetrates the body center, and inversion charge exists throughout the body. In contrast to the bulk transistors, depending on device geometry, the potential of the body center of undoped body devices could be higher than the surface in weak inversion regime and the current ows through the center-part of the device instead of surface. Several crucial parameters (e.g. Sub-threshold slope) sometimes become more dependable on the potential of body center rather than the surface. Hence the body-center potential should also be modeled correctly along with the surface-potential for accurate calculation of inversion charge, threshold voltage and other related parameters of undoped body multi-gate transistors. Although several potential models for MG transistors have been proposed to capture the short channel behavior in the subthreshold regime but most of them are based on the crucial approximation of coverting the 2D Poisson’s equation into Laplace equation. This approximation holds good only at surface but breaks down at body center and in the moderate inversion regime. As a result all the previous models fail to capture the potential of body center correctly and remain valid only in weak-inversion regime. In this work we have developed semiclassical compact models for potential distribution for double gate (DG) and cylindrical Gate-All-Around (GAA) transistors. The models are based on the analytical solution of 2D Poisson’s equation in the channel region and valid for both: a) weak and strong inversion regimes, b) long channel and short channel transistors, and, c) body surface and center. Using the proposed model, for the first time, it is demonstrated that the body potential versus gate voltage characteristics for the devices having equal channel lengths but different body thicknesses pass through a single common point (termed as crossover point). Using the concept of “crossover point” the effect of body thickness on the threshold voltage of undoped body multi-gate transistors is explained. Based on the proposed body potential model, a new compact model for the subthreshold swing is formulated. Some other parameters e.g. inversion charge, threshold voltage roll-off etc are also studied to demonstrate the impact of body center potential on the electrostatics of multi gate transistor. All the models are validated against professional numerical device simulator.

Researcher : Biswajit Ray, M.Sc. Enginering (2008).

Interconnects constitute a dominant source of circuit delay for modern chip de- signs. As scaling of technology continues chip interconnects are also been shrinking down. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this thesis, a practical interconnect delay variational analysis technique is presented to facilitate efficient evaluation of wire performance variability. we model the interconnect process variability by converting the telegrapher equation with random coefficients into stochastic differential equation. We measured how accurately this conversion works to map process variations into the variability of the output delay. Later, we propose a novel and efficient algorithm for modeling interconnect- networks in the presence of process variation. We develop a method for delay analysis of interconnects considering the impact of Gaussian metal process variations. The resistance and capacitance of a distributed RC line are expressed as independent Gaussian random variables which are then used to compute the standard deviation of delay Probability Distribution Functions at all nodes in the interconnect network. We validate the accuracy of our approach against SPICE based Monte Carlo simulations while having greatly lowered the computational cost.

Researcher : Sivakumar Bondada, M.E. Micro (2008).

The Tunnel Field Effect Transistor (TFET) with sub-60mV/decade Sub-threshold slope and extremely high ION/IOFF ratio has attracted enough attention for low standby power (LSTP) applications where the battery life is very important. So far research in this area has been limited to numerical simulation and experimental analysis. It is however extremely necessary to develop compact models for TFET in order to use them in nano-scale integrated circuit design and simulation. In this work, for the first time, we develop analytical Sub-threshold slope model for n-channel double gate TFET (nDGTFET). Unlike conventional FETs, current in TFET is mainly controlled by the band-to-band tunneling mechanism at source/channel interface. As the total drain cur- rent is proportional to band-to-band generation rate, the main challenge in the present work is to find an explicit relationship between average electric field over the tunneling path and the applied gate voltage under nonlocal tunneling condition. Two dimensional Poisson’s equation (with Laplace approximation) is first solved in a rectangular coordi- nate system in order to obtain analytical expression for electron energy distribution over the channel region. Kane’s Model [J. Phy. Chem. Solids 12(181) 1959] for band-to-band tunneling along with some analytical approximation techniques are then used to derive the expression for the Sub-threshold slope under nonlocal tunneling conditions. This Sub-threshold slope model is verified against professional numerical device simulator (MEDICI) for different device geometries. Being an asymmetric device, TFET fabrication suffers from source misalignment with gate. As the doping in source and drain-gate are different, conventional-FET- like self-aligned gate stack formation is not possible for TFET. Such misalignment, at source side, seriously degrades the performance of TFETs. To overcome this problem, in this work we explore the possibility of using “gate replacement” technique for TFET fabrication. We first develop process flow for single gate bulk nTFET, and then we extend it to n-channel double gate TFET (nDGTFET) using modified FinFET process. Good alignments between source and gate are observed with TCAD-simulations in both the cases.

Researcher : Ramesha A, M.Sc. Engineering (2008).

Continuous downscaling of CMOS technology has led to immense improvements in its performance. However, the switching characteristics of the present day MOSFET switch are far from the ideal one. For the Ideal switch the sub-threshold swing is zero and this leads to zero off-state current. This off-state current is the most crucial parameter for the low standby power applications (e.g. cellular phone) as it determines the battery life of the device. The minimum value of the sub-threshold swing of today’s MOSFET is physically limited to 60mV/decade at room temperature due to the drift-diffusion mode of carrier transport. In fact in ultra-short channel MOSFET the sub-threshold swing is further deteriorated due to several parasitic effects (e.g., punch through, short channel effects etc). Therefore for future low standby power application one requires alternative MOSFET architecture which uses different type of carrier transport mechanism. The aim of this thesis is to explore the various available options and to come up with a technology which is CMOS compatible and solves the problem of increased leakage for low standby power applications. The Tunnel Field Effect Transistor (TFET) with perfect saturation in the output characteristics, sub-60mV/decade subthreshold swing and extremely high ION/IOFF ratio has attracted a lot of attention for such applications. However, due to extremely low IOFF , even though it has a very good ION/IOFF ratio, it fails to meet the technology requirements of ION. To overcome this problem of low ION, in this work, we have proposed a new Tunnel FET architecture with SiGe layer at the source end. The improvement in ION is achieved by modulating the bandgap at the tunneling junction by varying the Ge mole fraction in the SiGe layer. By the use of 2D device simulation, we demonstrate that the proposed device is scalable upto channel lengths as small as 30 nm. Also, the device becomes nearly free from DIBL as the germanium mole fraction is increased. A CMOS compatible process flow to fabricate the proposed device is discussed. The compatibility of the process flow with the standard CMOS process makes the proposed device highly attractive for future low stand-by power applications.

Researcher : Nayan Bhogilal Patel, M.Sc. Engineering (2007).

As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits, many novel device structures are being extensively explored. Among them, the Silicon Nanowire Field Effect Transistor (Si- NWFET) has attracted broad attention from both the semiconductor industry and academia. Currently, there is intense interest in one dimensional silicon nanowires due to their excellent transport properties, compact size and compatibility with silicon technology. In nanoscale regime, it has become extremely important and essential to have quantum mechanical approach based simulation techniques to understand the working and performance limits of Si-NWFET. One such approach is Non-Equilibrium Green’s Function (NEGF) formalism. NEGF approach provides a rigorous description of quantum transport and scattering effects. In this work, the electrostatics and carrier dynamics of Si-NWFET, the most promising device structure in nanoscale regime have been studied. The scaling of a few key device parameters have been carried out to observe the variations in the properties of Si-NWFET in nanoscale regime. The quantum mechanical effects on electrostatics and carrier transport in Si-NWFETs have been simulated and studied using quantum mechanical simulators (provided by nanohub.org ). The comparison has been made between the simulation results obtained from professional device simulator (Sentaurus Device), which uses the semiclassical transport analysis and quantum mechanical simulator for multigate ultra thin body devices(Double gate-MOSFET and Si-NWFET) and observed the essential of quatum mechanical simulation in nanoscale regime. The Si-NWFET with rectangular and circular channel were simulated to compare the device characteristics. Finally, the performance of Si-NWFET is compared with Double gate-MOSFET.

Researcher : Shubhakar,M.E. Micro (2007).

Single electronics has attracted a lot of attention as an emerging nanotechnology due to its ultra low power dissipation, new functionalities, nano feature size and CMOS compatible fabrication process. It is imperative to explore the feasibility of using any new technology to build logic gates. In this thesis, a compact model for noise margins (NM) of SET Logic is developed which is a function of device capacitances and background charge (ζ). Noise margin is then used as a metric to evaluate the robustness of SET logic against ζ, temperature, variation of SET parameters (CT and CG), and energy quantization of the dot. It is shown that choosing ζ = CT=CG = 1/3, maximizes NM . An estimate of the maximum tolerable ζ, can be obtained and is shown to be equal to ±0:03e. The effect of energy quantization is studied through simulations and is found to degrade SET Logic performance. Finally the effect of mismatch in device parameters (CT and CG) on NM is studied through exhaustive simulations, which indicate that α Є [0.3, 0.4] for maximum robustness. It is also observed that mismatch can have a huge impact on static power.

Researcher : Chaitanya Sathe, M.E. Micro (2007).