Researcher: Madhuchhanda Brahma (2019)

With the passage of time the semiconductor research community around the globe has progressed from a nearly four decades of dominating Silicon research to look for newer transistor materials, in the pursuit of more operating speed along with reduced power, area and cost. Low effective mass materials like III-V compounds are the best examples of such transistor materials. In order to use those materials in real life transistor design and electronic applications, an engineer must have a set of mathematical models ready to use – which accurately predict various electronic characteristics of the devices. Therefore the development of canonical compact models for low effective mass channel material transistors is of prime importance for bringing these wonder materials into real life use.

Compact modeling is necessarily the art of translating the highly cumbersome and complicated physics within an electronic device into a set of predictable, portable, robust and computationally efficient analytical equations – that can be used in real-time circuit design. Existing compact models on low effective mass channel materials have a number of critical limitations, e.g. dealing with only symmetric oxide thickness, excessive use of unphysical approaches and empirical fitting parameters etc. Through our work – for the first time a fully physical, robust, portable compact model of low effective mass channel Common Double Gate MOSFET has been proposed and implemented. This compact model is a combination of accurate yet computationally efficient Surface Potential Equation (SPE) having analytical solution of coupled Schrodinger-Poisson equation; a Quantum Drift-Diffusion (QDD) based current transport and terminal charge model along with inclusion of DIBL effect. Due to enormous quantum confinement, the quasi-Fermi levels of each energy sub-band remains distant from each other because the carriers remain in the thermal equilibrium in their respective sub-bands. This segregation in quasi-Fermi levels, caused by strong quantum confinement, severely affects the transport in the semiconductor channel – thus changing the transport from normal Drift-Diffusion as in Silicon MOSFETs to QDD in low effective mass channel MOSFETs.

The model development starts with a couple of rightfully logical assumptions, which are compensated in subsequent stages to the best possible extent. The wave-function corresponding to a particular sub-band in the channel is derived only under flat-band condition. It is used throughout in model development, and in the last stage the model is compensated by introducing an analytically derived correction factor. Individual sub-band energies are also derived initially under ground-state, and in later stages their bias dependence is addressed through perturbation technique. While modeling the transport, channel charge density for an individual sub-band is shown to be varying linearly with sub-band energy along the channel, resulting into a square law current versus channel charge density model. The uniqueness of the proposed model lies in its precise handling of multiple issues like asymmetry in oxide layer thickness, wave function penetration, bias dependent diffusivity, Quantum Drift-Diffusion transport, multi-sub-band carrier occupancy and wide range of material effective mass, device thickness along with input voltages – without ever using a single unphysical polynomial fitting or empirical constant, while preserving the mathematical lucidity of industry standard Silicon MOSFET models. The proposed model is validated against numerical TCAD simulation for various device geometries, oxide asymmetries, material properties and successfully implemented in professional circuit simulator through its verilog-A interface. Through this work, the fundamental Quantum Drift-Diffusion transport is for the first time introduced into circuit simulation, which earlier was limited within device simulation only – thus opening the possibility of designing circuits using low effective mass materials.

Researcher: Ananda Sankar Chakraborty (2019)

In recent years, the use of first-principles based atomistic modeling technique has become extremely popular to gain better insights on the various locally modulated electronic properties of nano materials and structures. Atomistic modeling offers the benefit of predicting crystal structures, visualizing orbital distribution and electron density, as well as understanding material properties which are hard to access experimentally.

The single layer MoS2 has emerged as a suitable choice for the next generation nano devices, owing to its distinctive electrical, optical and mechanical properties like, better electrostatics, increased photo luminescence, higher mechanical flexibility, etc. The real- ization of decananometer scale digital switches with the single layer MoS2 as the channel may provide many significant advantages such as, high On/Off current ratio, excellent electrostatic control of the gate, low leakage, etc.

However, there are quite a few critical issues such as, forming low resistance source/drain contacts, achieving higher effective mobility, ensuring large scale controlled growth, etc. which need to be addressed for successful implementation of the atomically thin transis- tors in integrated circuits. Recent experimental demonstration showing the coexistence of metallic and semiconducting phases in the same monolayer MoS2, has attracted much attention for its use in ultra-low contact resistance-MoS2 transistors. Howbeit, the elec- tronic structures of the metallic-to-semiconducting phase boundaries, which appear to dictate the carrier injection in such transistors, are not yet well understood.

In this work, we first develop the geometrically optimized atomistic models of the 2H- 1T′ hetero-phase structures with two distinct phase boundaries, β and γ. We then apply density functional theory to calculate the electronic structures for those optimized geome- tries. Furthermore, we employ non equilibrium Green’s function formalism to evaluate the transmission spectra and the local density of states in order to assess the Schottky barrier nature of the phase boundaries.

Nonetheless, the symmetry of the source-channel and drain-channel junction, is a unique property of a metal-oxide semiconductor field effect transistor (MOSFET), which needs to be preserved while realizing sub-10 nm channel length devices using advanced technology. Employing experimental-findings-driven atomistic modeling technique, we demonstrate that such symmetry might not be preserved in an atomically thin phase-engineered MoS2- based MOSFET. It originates from the two distinct atomic patterns at phase boundaries (β and β*) when the semiconducting phase (channel) is sandwiched between the two metallic phases (source and drain).

Next, using first principles based quantum transport calculations we demonstrate that, due to the clusterization of “Mo” atoms in 1T′ MoS2, the transmission along the zigzag direction is significantly higher than that in the armchair direction. Moreover, to achieve excellent impedance matching with various metal contacts (such as, “Au”, “Pd”, etc.), we further develop the atomistic models of metal-1T′ MoS2 edge contact geometries and compute their resistance values.

Other than the charge carrier transport, analysing the heat transport across the channel is also crucial in designing the ultra-thin next generation transistors. Hence, in this thesis work, we have investigated the electro-thermal transport properties of single layer MoS2, in quasi ballistic regime. Besides the perfect monolayer in its pristine form, we have also considered various line defects which have been experimentally observed in mechanically exfoliated MoS2 samples. Furthermore, a comprehensive study on the phonon thermal conductivity of a suspended monolayer MoS2, has been incorporated in this thesis.

The studies presented in this thesis could be useful for understanding the carrier transport in atomically thin devices and designing the ultra-thin next generation transistors.

Researcher: Dipankar Saha (2017)

Moore’s law falls short of down-scaling the technology nodes in the sub decananometer regime and producing effective high performance logic devices. So, the ITRS trend expects to conceptualize novel device structure such as extremely thin Silicon on insulator (ETSOI), multi gate FETs (MuGFETs) or FinFETs and explore new 2D materials as a suitable channel materials for FET’s. Post the exfoliation of monolayer graphene, many 2D materials are being utilized to replace the bulk silicon as the channel material, viz., TMD’s, black phosphorous etc. Though semiconductive atomically-thin layered materials based FET may provide exceptional electrostatic integrity, yet the ON current in the experimental devices are low in comparison to the required one. Significant Schottky barrier height (SBH) at the metal-semiconductor interface at source/drain terminals is identified as one of the possible reasons for low values of ON current. Many techniques are demonstrated experimentally as well as novel 2D materials are explored with an aim to lessen the SBH and enhance the values of ON current. Nonetheless, the interface chemistry leading to the reduction of SBH is not probed effectively since accessing this phenomena experimentally at atomic level is in altogether quite challenging. Thereby, in the present thesis, a comprehensive and thorough study is done to develop a theoretical perspective of various 2D material – metal interface by employing Density Functional Theory (DFT) which is efficaciously applied earlier to study the graphene-metal contact. The study is organized by following entirely a systematic approach: creation of optimized geometry for the interface, estimation of an equilibrium interlayer distance, analysis of potential barrier at the interface, exploration of charge transfer and interface dipole, investigation of orbital hybridization and finally evaluating the SBH. Exchange correlation functions, pseudopotentials and basis sets are chosen appropriately and very carefully for each interface structure to produce the precise electronic structures. Firstly we outline our methodology to study a 2D material-metal contact. The first application of our methodology is for an interface formed between the metal (gold, palladium and titanium) and puckered honeycomb monolayer of black phosphorous (i.e. phosphorene). Following it, we analyze a graphene inserted MoS2-metal interface (titanium, silver, ruthenium, gold and platinum), ranging from metal with low work function to high work function. Furthermore, we continue our study for p-type niobium doped MoS2 and its contact with gold. Apart from p type TMD, n-type chlorine doped WS2 and its contact with gold and palladium is also examined for this study. Doping graphene with BN is one among the possible choices to open band gap in pristine graphene. In the next part we study these materials and analyze various defects such as stone-wales and vacancy on the performance of boron-nitride embedded graphene nanoribbon transistor.

Researcher : Anuja Chanana (2016)

Compact Models are the physically based accurate mathematical description of the circuit elements, which are computationally efficient enough to be incorporated in circuit simulators so that the outcome becomes useful for the circuit designers. Since the multi-gate MOSFETs have appeared as replacements for bulk-MOSFETs in sub-32nm technology nodes, efficient compact models for these new transistors are required for their successful utilization in integrated circuits. Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this work we explore the possibility of developing models without this approximation, while preserving the computational efficiency at the same level. Such effort aims to generalize the compact model and also to capture the oxide thickness asymmetry effect, which might prevail in practical devices due to process uncertainties and thus affects the device performance significantly. However solution to this modeling problem is nontrivial due to the bias-dependent asymmetric nature of the electrostatic. Using the ‘single implicit equation based Poisson solution’ and the ‘unique quasi-linear relationship between the surface potentials’, previous researchers of our laboratory have reported the ‘core’ model for such asymmetric CDG MOSFET. In this work effort has been put to include Non-Quasistatic (NQS) effects, different small-geometry effects, and noise model to this ‘core’, so that the model becomes suitable for practical applications. It is demonstrated that the quasi-linear relationship between the surface potentials remains preserved under NQS condition, in the presence of all small geometry effects. This property of the device along with some other new techniques is used to develop the model while keeping the mathematical complexity at the same level of the models reported for the symmetric devices. Proposed model is verified against TCAD simulation for various device geometries and successfully implemented in professional circuit simulator. The model passes the source/drain symmetry test and good convergence is observed during standard circuit simulations.

Researcher : Neha Sharan (2014)

Due to the aggressive downscaling of the CMOS technology, power and current densities are increasing inside the chip. The limiting current conduction capacity (106 Acm-2) and thermal conductivity (201 Wm-1K-1 for Al and 400 Wm-1K-1 for Cu) of the existing interconnects materials has given rise to different electro-thermal issues such as hot-spot formation, electromigration, etc. Exploration of new materials with high thermal conductivity and current conduction has thus attracted much attention for future integrated circuit technology. Among all the elemental materials, carbon nanomaterials (graphene and carbon nanotube) possess exceptionally high thermal (600-7000 Wm-1K-1) and current ~ 108 – 109 Acm-2) conduction properties at room temperature, which makes them potential candidate for interconnect materials. At the same time development of efficient energy harvesting techniques are also becoming important for future wireless autonomous devices. The excess heat generated at the hot-spot location could be used to drive an electronic circuit through a suitable thermoelectric generator. As the Seebeck coefficient of graphene is reported to be the highest among all elementary semiconductors, exploration of thermoelectric properties of graphene is very important. This thesis investigates the electrothermal and thermoelectric properties of metallic single walled carbon nanotube (SWCNT) and single layer graphene (SLG) for their possible applications in thermal management in next generation integrated circuits. A closed form analytical solution of Joule-heating equation in metallic SWCNTs is thus proposed by considering a temperature dependent lattice thermal conductivity (κ) on the basis of three-phonon Umklapp, mass-difference and boundary scattering phenomena. The solution of which gives the temperature profile over the SWCNT length and hence the location of hot-spot (created due to the self-heating inside the chip) can be predicted. This self-heating phenomenon is further extended to estimate the electromigration performance and mean-time-to-failure of metallic SWCNTs. It is shown that metallic SWCNTs are less prone to electromigration. To analyze the electro-thermal effects in a suspended SLG, a physics-based flexural phonon dominated thermal conductivity model is developed, which shows that κ follows a T1.5 and T-2 law at lower (less than 300) K and higher temperature respectively in the absence of isotopes (C13 atoms). However in the presence of isotopic impurity, the behavior of κ sharply deviates from T-2 at higher temperatures. The proposed model of κ is found to be in excellent match with the available experimental data over a wide range of temperatures and can be utilized for an efficient electro-thermal analysis of encased/supported graphene. By considering the interaction of electron with in-plane and flexural phonons in a doped SLG sheet, a physics-based electrical conductance (σ) model of SLG under self-heating effect is also discussed that particularly exhibits the variation of electrical resistance with temperature at different current levels and matches well with the available experimental data. To investigate the thermoelectric performance of a SLG sheet, analytical models for Seebeck effect coefficient (SB) and specific heat (Cph) are developed, which are found to be in good agreement with the experimental data. Using those analytical models, it is predicted that one can achieve a thermoelectric figure of merit (ZT) of ~ 0.62 at room temperature by adding isotopic impurities (C13 atoms) in a degenerate SLG. Such prediction shows the immense potential of graphene in waste-heat recovery applications. Those models for σ, κ, SB and Cph are further used to determine the time evolution of temperature distribution along suspended SLG sheet through a transient analysis of Joule-heating equation under the Thomson effect. The proposed methodology can be extended to analyze the graphene heat-spreader theory and interconnects and graphene based thermoelectrics.

Researcher : Rekha Verma (2013)

 Technology scaling beyond Moore’s law demands cutting-edge solutions of the gate length scaling in sub-10 nm regime for low power high speed operations. Recently SOI technology has received considerable attention, however manufacturable solutions in sub-10 nm technologies are not yet known for future nanoelectronics. Therefore, to continue scaling in sub-10 nm region, new one (1D) and two dimensional (2D) “nano-materials” and engineering are expected to keep its pace. However, significant challenges must be overcome for nano-material properties in carrier transport to be useful in future silicon nanotechnology. Thus, it is very important to understand and modulate their electronic band structure and transport properties for low power nanoelectronics applications. This thesis tries to provide solutions for some problems in this area. In recent times, one dimensional Silicon nanowire has emerged as a building block for the next generation nano-electronic devices as it can accommodate multiple gate transistor architecture with excellent electrostatic integrity. However as the experimental study of various energy band parameters at the nanoscale regime is extremely challenging, usually one relies on the atomic level simulations, the results of which are at par with the experimental observations. Two such parameters are the band gap and effective mass, which are of pioneer importance for the understanding of the current transport mechanism. Although there exists a large number of empirical relations of the band gap in relaxed Silicon nanowire, however there is a growing demand for the development of a physics based analytical model to standardize different energy band parameters which particularly demands its application in TCAD software for predicting different electrical characteristics of novel devices and its strained counterpart to increase the device characteristics significantly without changing the device architecture. The first part of this work reports the analytical modeling of energy band gap and electron transport effective mass of relaxed and strained Silicon nanowires in various crystallographic directions for future nanoelectronics. The technology scaling of gate length in beyond Moorefs law devices also demands the SOI body thickness, Tsi–> The investigations on ultrathin body materials also call for a need to explore new 2D materials with finite band gap and their various nanostructures for future nanoelectronic applications in order to replace conventional Silicon. In the third part of this report, we have investigated the electronic and dielectric properties of semiconducting layered Transition metal dichalcogenide meterials (MX2) (M = Mo, W; X = S, Se, Te) which has recently emerged as a promising alternative to Si as channel materials for CMOS devices. Five layered MX2 materials (except WTe2) in their 2D sheet and 1D nanoribbon forms are considered to study the real and imaginary band structure of those MX2 materials by atomistic simulations. Studying the complex dispersion properties, it is shown that all the five MX2 support direct BTBT in their monolayer sheet forms and offer an average ON current and subthreshold slope of 150 µA/µm and 4 mV/dec, respectively. However, only the MoTe2 support direct BTBT in its nanoribbon form, whereas the direct BTBT possibility in MoS2 and MoSe2 depends on the number of layers or applied uniaxial strain. WX2 nanoribbons are shown to be non-suitable for efficient TFET operation. Reasonably high tunneling current in these MX2 shows that these can take advantage over conventional Silicon in future tunnel field effect transistor applications.

Researcher : Ram Krishna Ghosh (2013)

Independent double gate (IDG) metal oxide semiconductor field effect transistor (MOSFET) has received considerable attention in recent years owing to its ability to modulate threshold voltage and transconductance dynamically. Due to the asymmetric nature of electrostatic, developing efficient compact models for such devices is a daunting task in comparison to the symmetric double gate transistor. The thesis tries to provide solutions for some problems in this area. The modeling of the long channel potential by solving the one-dimensional Poisson equation (PE) is the most fundamental step towards developing surface-potential-based core compact models for such transistors. Previous techniques used for solving the one-dimensional Poisson equation rigorously for the long channel asymmetric and independent double gate transistors result in potential models that involve multiple inter-coupled implicit equations. As these equations need to be solved self-consistently, such potential models are clearly inefficient for compact modeling. This work reports a different rigorous technique for solving the same Poisson equation by which one can obtain the potential profile of a generalized independent double gate transistor that involves a single implicit equation. The proposed Poisson solution is shown to be at-least five times computationally more efficient for circuit simulation than the previous solutions. Developing efficient models for terminal charges is another crucial step towards compact modeling. In this work we show the limitations of the traditional charge linearization techniques for modeling terminal charges of the IDG MOSFETs. We propose a new charge linearization technique in order to model the terminal charges and transcapacitances of the IDG MOSFETs. We report two different types of quasi-static large signal models for the long channel device. In the first type, the terminal charges are expressed as closed form functions of source and drain end inversion charge densities and found to be accurate when the potential distribution at source end of the channel is hyperbolic in nature. The second type, which is found to be accurate in all regimes of operations, is based on quadratic spline collocation technique and requires the input voltage equation to be solved two more times apart from the source and drain end. Proposed model has been successfully implemented in professional circuit simulator. Voltage controlled oscillators (VCOs) based on metal oxide semiconductor (MOS) varactors have become an integral part of RF communication circuits. An independently controlled double gate based MOS capacitor can bring out new functionalities, which could be interesting for RF circuit applications. For the first time, this work, explores the characteristics of MOS capacitor controlled by independent double gates by numerical simulation and analytical modeling for its possible use in RF circuit design as a varactor. By numerical simulation it is shown how the quasi-static and non-quasi-static characteristics of the first gate capacitance could be tuned by the second gate biases. Analytical solution of complete (considering both electron and hole concentration) Poisson equation (PE) is proposed. A new set of input voltage equations (IVEs) for independent double gate MOSFET are proposed by solving the governing bipolar Poisson equation rigorously. The proposed IVEs, involve the Legendre’s incomplete elliptic integral of the first kind andJacobian elliptic functions and are valid from accumulation to inversion regimes. As Legendre’s incomplete elliptic integral of first kind and Jacobian elliptic functions are computationally expensive, hence I also propose a semi-empirical solution using previous analytical solution of the PE for IDG MOS capacitor considering only electron/hole. Proposed models, which are valid from accumulation to inversion, are shown to have excellent agreement with numerical simulation for practical bias conditions.

Researcher : Pankaj Kumar Thakur (2013)

For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology scaling beyond 22nm node, it is clear that conventional bulk-MOSFET needs to be replaced by new device architectures, most promising being the Multiple-Gate MOSFETs MuGFET). Intel in mid 2011 announced the use of bulk Tri-Gate FinFETs in 22nm high volume logic process for its next-gen IvyBridge Microprocessor. It is expected that soon other semiconductor companies will also adopt the MuGFET devices. As like bulk- MOSFET, an accurate and physical compact model is important for MuGFET based circuit design. Compact modeling effort for MuGFET started in late nineties with planar double gate MOSFET (DGFET), as it is the simplest structure that one can conceive for MuGFET devices. The models so far proposed for DG MOSFETs are applicable for common gate symmetric DG (SDG) MOSFETs where both the gates have equal oxide thick- nesses. However, for practical devices at nanoscale regime, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. At the same time, Independently controlled DG (IDG) MOSFETs have gained tremendous attention owing to its ability to modulate threshold voltage and transconductance dynamically. Due to the asymmetric nature of the electrostatic, developing efficient compact models for asymmetric/independent DG MOSFET is a daunting task. In this thesis effort has been put to provide some solutions to this challenge. We propose simple surface-potential based compact terminal charge models, applicable for Asymmetric Double gate MOSFETs (ADG) in two configurations 1) Common-gate 2) Independent-gate. The charge model proposed for the common-gate ADG (CDG) MOSFET is seamless between the symmetric and asymmetric devices and utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and can be easily implemented in any circuit simulator and extendable to short-channel devices. The charge model proposed for independent ADG (IDG) MOSFET is based on a novel piecewise linearization technique of surface potential along the channel. We show that the conventional “charge linearization techniques that have been used over the years in advanced compact models for bulk and double-gate (DG) MOSFETs are accurate only when the channel is fully hyperbolic in nature or the effective gate voltages are same. For other bias conditions, it leads to significant error in terminal charge computation. We demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel for a particular bias condition actually dictates if the conventional charge linearization technique could be applied or not. We propose a piecewise linearization technique that segments the channel into multiple sections where in each section, the assumption of quasi-linear relationship between the surface potentials remains valid. The cumulative sum of the terminal charges obtained for each of these channel sections yield terminal charges of the IDG device. We next present our work on modeling the non-ideal scenarios like presence of body doping in CDG devices and the non-planar devices like Tri-gate FinFETs. For a fully depleted channel, a simple technique to include body doping term in our charge model for CDG devices, using a perturbation on the effective gate voltage and correction to the coupling factor, is proposed. We present our study on the possibility of mapping a non-planar Tri-gate FinFET onto a planar DG model. In this framework, we demon- strate that, except for the case of large or tall devices, the generic mapping parameters become bias-dependent and an accurate bias-independent model valid for geometries is not possible. An efficient and robust “Root Bracketing Method” based algorithm for computation of surface potential in IDG MOSFET, where the conventional Newton-Raphson based techniques are inefficient due to the presence of singularity and discontinuity in input voltage equations, is presented. In case of small asymmetry for a CDG devices, a simple physics based perturbation technique to compute the surface potential with computational complexity of the same order of an SDG device is presented next. All the models proposed show excellent agreement with numerical and Technology Computer-Aided Design (TCAD) simulations for all wide range of bias conditions and geometries. The models are implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.

Researcher : J. Srivatsava (2013)

Although scaling of CMOS (Complementary Metal Oxide Semiconductor) technology has been predicted to continue for another decade, novel technological solutions are required to overcome the fundamental limitations of the decananometer MOS transistors. Single Electron Transistor (SET) has attracted attention mainly because of its unique Coulomb blockade oscillations characteristics, ultra low power dissipation and nano-scale feature size. Despite the high potential, due to some intrinsic limitations (e.g., very low current drive) it will be very difficult for SET to compete head-to-head with CMOS’s large-scale infrastructure, proven design methodologies, and economic predictability. Nevertheless, the characteristics of SET and MOS transistors are quite complementary. SET advocates low-power consumption and new functionality (related to the Coulomb blockade oscillations), while CMOS has advantages like high-speed driving and voltage gain that can compensate the intrinsic drawbacks of SET. Therefore, although a complete replacement of CMOS by single-electronics is unlikely in the near future, it is also true that combining SET and CMOS one can bring out new functionalities, which are un-mirrored in pure CMOS technology. As the hybridization of CMOS and SET is gaining popularity, silicon SETs are appearing to be more promising than metallic SETs for their possible integration with CMOS. SETs are normally studied on the basis of the classical Orthodox Theory, where quantization of energy states in the island is completely ignored. Though this assumption greatly simplifies the physics involved, it is valid only when the SET is made of metallic island. As one cannot neglect the quantization of energy states in a semiconductive island, it is extremely important to study the effects of energy quantization on hybrid CMOS-SET integrated circuits. The main objective of this thesis is to understand energy quantization effects on SET by numerical simulations, develop simple analytical models that can capture the energy quantization effects, analyze the effects of energy quantization on SET logic inverter, and finally, develop a CAD framework for CMOS-SET co-simulation and to study the effect on energy quantization on hybrid circuits using that framework. In this work the widely accepted SIMON Monte Carlo (MC) simulator for single electron devices and circuits is used to study the effect of energy quantization. So far SIMON has been used to study SETs having metallic island. In this work, for the first time, we have shown how one can use SIMON to analyze SET island properties having discrete energy states. It is shown that energy quantization mainly changes the Coulomb Blockade region and drain current of SET devices and thus affects the noise margin, power dissipation, and the propagation delay of SET logic inverter. A new model for the noise margin of SET inverter is proposed, which includes the energy quantization term. Using the noise margin as a metric, the robustness of SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termed as “Quantization Threshold”) that an SET inverter logic circuit can withstand before its noise margin falls below a specified tolerance level. It is found that SET inverter designed with CT : CG = 0.366 (where CT and CG are tunnel junction and gate capacitances respectively) offers maximum robustness against energy quantization. Then the effects of energy quantization are studied for Current biased SET (CBS), which is an integral part of almost all hybrid CMOS-SET circuits. It is demonstrated that energy quantization has no impact on the gain of the CBS characteristics though it changes the output voltage levels and oscillation periodicity. The effects of energy quantization are further studied for two circuits: Negative Differential Resistance (NDR) and Neurone Cell, which use CBS. A new model for the conductance of NDR characteristics is also formulated that includes the energy quantization term. A novel CAD framework is then developed for CMOS-SET co-simulation, which uses MC simulator for SET devices along with conventional SPICE. Using this framework, the effects of energy quantization are studied for some hybrid circuits, namely, SETMOS, multiband voltage filter, and multiple valued logic circuits. It is found that energy quantization degrades the performance of hybrid circuit, which could be compensated by properly tuning the bias current of SET devices. Though this study is primarily done by exhaustive MC simulation, effort has also been put to develop first order compact model for SET that includes energy quantization effects. Finally it is demonstrated that one can predict the SET behavior under energy quantization with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

Researcher : Surya Shankar Dan (2009)

Researcher: Madhuchhanda Brahma (2019)

With the passage of time the semiconductor research community around the globe has progressed from a nearly four decades of dominating Silicon research to look for newer transistor materials, in the pursuit of more operating speed along with reduced power, area and cost. Low effective mass materials like III-V compounds are the best examples of such transistor materials. In order to use those materials in real life transistor design and electronic applications, an engineer must have a set of mathematical models ready to use – which accurately predict various electronic characteristics of the devices. Therefore the development of canonical compact models for low effective mass channel material transistors is of prime importance for bringing these wonder materials into real life use.

Compact modeling is necessarily the art of translating the highly cumbersome and complicated physics within an electronic device into a set of predictable, portable, robust and computationally efficient analytical equations – that can be used in real-time circuit design. Existing compact models on low effective mass channel materials have a number of critical limitations, e.g. dealing with only symmetric oxide thickness, excessive use of unphysical approaches and empirical fitting parameters etc. Through our work – for the first time a fully physical, robust, portable compact model of low effective mass channel Common Double Gate MOSFET has been proposed and implemented. This compact model is a combination of accurate yet computationally efficient Surface Potential Equation (SPE) having analytical solution of coupled Schrodinger-Poisson equation; a Quantum Drift-Diffusion (QDD) based current transport and terminal charge model along with inclusion of DIBL effect. Due to e
normous quantum confinement, the quasi-Fermi levels of each energy sub-band remains distant from each other because the carriers remain in the thermal equilibrium in their respective sub-bands. This segregation in quasi-Fermi levels, caused by strong quantum confinement, severely affects the transport in the semiconductor channel – thus changing the transport from normal Drift-Diffusion as in Silicon MOSFETs to QDD in low effective mass channel MOSFETs.

The model development starts with a couple of rightfully logical assumptions, which are compensated in subsequent stages to the best possible extent. The wave-function corresponding to a particular sub-band in the channel is derived only under flat-band condition. It is used throughout in model development, and in the last stage the model is compensated by introducing an analytically derived correction factor. Individual sub-band energies are also derived initially under ground-state, and in later stages their bias dependence is addressed through perturbation technique. While modeling the transport, channel charge density for an individual sub-band is shown to be varying linearly with sub-band energy along the channel, resulting into a square law current versus channel charge density model. The uniqueness of the proposed model lies in its precise handling of multiple issues like asymmetry in oxide layer thickness, wave function penetration, bias dependent diffusivity, Quantum
Drift-D
iffusion transport, multi-sub-band carrier occupancy and wide range of material effective mass, device thickness along with input voltages – without ever using a single unphysical polynomial fitting or empirical constant, while preserving the mathematical lucidity of industry standard Silicon MOSFET models. The proposed model is validated against numerical TCAD simulation for various device geometries, oxide asymmetries, material properties and successfully implemented in professional circuit simulator through its verilog-A interface. Through this work, the fundamental Quantum Drift-Diffusion transport is for the first time introduced into circuit simulation, which earlier was limited within device simulation only – thus opening the possibility of designing circuits using low effective mass materials.

Researcher: Ananda Sankar Chakraborty (2019)

In recent years, the use of first-principles based atomistic modeling technique has become extremely popular to gain better insights on the various locally modulated electronic properties of nano materials and structures. Atomistic modeling offers the benefit of predicting crystal structures, visualizing orbital distribution and electron density, as well as understanding material properties which are hard to access experimentally.

The single layer MoS2 has emerged as a suitable choice for the next generation nano devices, owing to its distinctive electrical, optical and mechanical properties like, better electrostatics, increased photo luminescence, higher mechanical flexibility, etc. The real- ization of decananometer scale digital switches with the single layer MoS2 as the channel may provide many significant advantages such as, high On/Off current ratio, excellent electrostatic control of the gate, low leakage, etc.

However, there are quite a few critical issues such as, forming low resistance source/drain contacts, achieving higher effective mobility, ensuring large scale controlled growth, etc. which need to be addressed for successful implementation of the atomically thin transis- tors in integrated circuits. Recent experimental demonstration showing the coexistence of metallic and semiconducting phases in the same monolayer MoS2, has attracted much attention for its use in ultra-low contact resistance-MoS2 transistors. Howbeit, the elec- tronic structures of the metallic-to-semiconducting phase boundaries, which appear to dictate the carrier injection in such transistors, are not yet well understood.

In this work, we first develop the geometrically optimized atomistic models of the 2H- 1T′ hetero-phase structures with two distinct phase boundaries, β and γ. We then apply density functional theory to calculate the electronic structures for those optimized geome- tries. Furthermore, we employ non equilibrium Green’s function formalism to evaluate the transmission spectra and the local density of states in order to assess the Schottky barrier nature of the phase boundaries.

Nonetheless, the symmetry of the source-channel and drain-channel junction, is a unique property of a metal-oxide semiconductor field effect transistor (MOSFET), which needs to be preserved while realizing sub-10 nm channel length devices using advanced technology. Employing experimental-findings-driven atomistic modeling technique, we demonstrate that such symmetry might not be preserved in an atomically thin phase-engineered MoS2- based MOSFET. It originates from the two distinct atomic patterns at phase boundaries (β and β*) when the semiconducting phase (channel) is sandwiched between the two metallic phases (source and drain).

Next, using first principles based quantum transport calculations we demonstrate that, due to the clusterization of “Mo” atoms in 1T′ MoS2, the transmission along the zigzag direction is significantly higher than that in the armchair direction. Moreover, to achieve excellent impedance matching with various metal contacts (such as, “Au”, “Pd”, etc.), we further develop the atomistic models of metal-1T′ MoS2 edge contact geometries and compute their resistance values.

Other than the charge carrier transport, analysing the heat transport across the channel is also crucial in designing the ultra-thin next generation transistors. Hence, in this thesis work, we have investigated the electro-thermal transport properties of single layer MoS2, in quasi ballistic regime. Besides the perfect monolayer in its pristine form, we have also considered various line defects which have been experimentally observed in mechanically exfoliated MoS2 samples. Furthermore, a comprehensive study on the phonon thermal conductivity of a suspended monolayer MoS2, has been incorporated in this thesis.

The studies presented in this thesis could be useful for understanding the carrier transport in atomically thin devices and designing the ultra-thin next generation transistors.

Researcher: Dipankar Saha (2017)

Moore’s law falls short of down-scaling the technology nodes in the sub decananometer regime and producing effective high performance logic devices. So, the ITRS trend expects to conceptualize novel device structure such as extremely thin Silicon on insulator (ETSOI), multi gate FETs (MuGFETs) or FinFETs and explore new 2D materials as a suitable channel materials for FET’s. Post the exfoliation of monolayer graphene, many 2D materials are being utilized to replace the bulk silicon as the channel material, viz., TMD’s, black phosphorous etc. Though semiconductive atomically-thin layered materials based FET may provide exceptional electrostatic integrity, yet the ON current in the experimental devices are low in comparison to the required one. Significant Schottky barrier height (SBH) at the metal-semiconductor interface at source/drain terminals is identified as one of the possible reasons for low values of ON current. Many techniques are demonstrated experimentally as well as novel 2D materials are explored with an aim to lessen the SBH and enhance the values of ON current. Nonetheless, the interface chemistry leading to the reduction of SBH is not probed effectively since accessing this phenomena experimentally at atomic level is in altogether quite challenging. Thereby, in the present thesis, a comprehensive and thorough study is done to develop a theoretical perspective of various 2D material – metal interface by employing Density Functional Theory (DFT) which is efficaciously applied earlier to study the graphene-metal contact. The study is organized by following entirely a systematic approach: creation of optimized geometry for the interface, estimation of an equilibrium interlayer distance, analysis of potential barrier at the interface, exploration of charge transfer and interface dipole, investigation of orbital hybridization and finally evaluating the SBH. Exchange correlation functions, pseudopotentials and basis sets are chosen appropriately and very carefully for each interface structure to produce the precise electronic structures. Firstly we outline our methodology to study a 2D material-metal contact. The first application of our methodology is for an interface formed between the metal (gold, palladium and titanium) and puckered honeycomb monolayer of black phosphorous (i.e. phosphorene). Following it, we analyze a graphene inserted MoS2-metal interface (titanium, silver, ruthenium, gold and platinum), ranging from metal with low work function to high work function. Furthermore, we continue our study for p-type niobium doped MoS2 and its contact with gold. Apart from p type TMD, n-type chlorine doped WS2 and its contact with gold and palladium is also examined for this study. Doping graphene with BN is one among the possible choices to open band gap in pristine graphene. In the next part we study these materials and analyze various defects such as stone-wales and vacancy on the performance of boron-nitride embedded graphene nanoribbon transistor.

Researcher : Anuja Chanana (2016)

Compact Models are the physically based accurate mathematical description of the circuit elements, which are computationally efficient enough to be incorporated in circuit simulators so that the outcome becomes useful for the circuit designers. Since the multi-gate MOSFETs have appeared as replacements for bulk-MOSFETs in sub-32nm technology nodes, efficient compact models for these new transistors are required for their successful utilization in integrated circuits. Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this work we explore the possibility of developing models without this approximation, while preserving the computational efficiency at the same level. Such effort aims to generalize the compact model and also to capture the oxide thickness asymmetry effect, which might prevail in practical devices due to process uncertainties and thus affects the device performance significantly. However solution to this modeling problem is nontrivial due to the bias-dependent asymmetric nature of the electrostatic. Using the ‘single implicit equation based Poisson solution’ and the ‘unique quasi-linear relationship between the surface potentials’, previous researchers of our laboratory have reported the ‘core’ model for such asymmetric CDG MOSFET. In this work effort has been put to include Non-Quasistatic (NQS) effects, different small-geometry effects, and noise model to this ‘core’, so that the model becomes suitable for practical applications. It is demonstrated that the quasi-linear relationship between the surface potentials remains preserved under NQS condition, in the presence of all small geometry effects. This property of the device along with some other new techniques is used to develop the model while keeping the mathematical complexity at the same level of the models reported for the symmetric devices. Proposed model is verified against TCAD simulation for various device geometries and successfully implemented in professional circuit simulator. The model passes the source/drain symmetry test and good convergence is observed during standard circuit simulations.

Researcher : Neha Sharan (2014)

Due to the aggressive downscaling of the CMOS technology, power and current densities are increasing inside the chip. The limiting current conduction capacity (106 Acm-2) and thermal conductivity (201 Wm-1K-1 for Al and 400 Wm-1K-1 for Cu) of the existing interconnects materials has given rise to different electro-thermal issues such as hot-spot formation, electromigration, etc. Exploration of new materials with high thermal conductivity and current conduction has thus attracted much attention for future integrated circuit technology. Among all the elemental materials, carbon nanomaterials (graphene and carbon nanotube) possess exceptionally high thermal (600-7000 Wm-1K-1) and current ~ 108 – 109 Acm-2) conduction properties at room temperature, which makes them potential candidate for interconnect materials. At the same time development of efficient energy harvesting techniques are also becoming important for future wireless autonomous devices. The excess heat generated at the hot-spot location could be used to drive an electronic circuit through a suitable thermoelectric generator. As the Seebeck coefficient of graphene is reported to be the highest among all elementary semiconductors, exploration of thermoelectric properties of graphene is very important. This thesis investigates the electrothermal and thermoelectric properties of metallic single walled carbon nanotube (SWCNT) and single layer graphene (SLG) for their possible applications in thermal management in next generation integrated circuits. A closed form analytical solution of Joule-heating equation in metallic SWCNTs is thus proposed by considering a temperature dependent lattice thermal conductivity (κ) on the basis of three-phonon Umklapp, mass-difference and boundary scattering phenomena. The solution of which gives the temperature profile over the SWCNT length and hence the location of hot-spot (created due to the self-heating inside the chip) can be predicted. This self-heating phenomenon is further extended to estimate the electromigration performance and mean-time-to-failure of metallic SWCNTs. It is shown that metallic SWCNTs are less prone to electromigration. To analyze the electro-thermal effects in a suspended SLG, a physics-based flexural phonon dominated thermal conductivity model is developed, which shows that κ follows a T1.5 and T-2 law at lower (less than 300) K and higher temperature respectively in the absence of isotopes (C13 atoms). However in the presence of isotopic impurity, the behavior of κ sharply deviates from T-2 at higher temperatures. The proposed model of κ is found to be in excellent match with the available experimental data over a wide range of temperatures and can be utilized for an efficient electro-thermal analysis of encased/supported graphene. By considering the interaction of electron with in-plane and flexural phonons in a doped SLG sheet, a physics-based electrical conductance (σ) model of SLG under self-heating effect is also discussed that particularly exhibits the variation of electrical resistance with temperature at different current levels and matches well with the available experimental data. To investigate the thermoelectric performance of a SLG sheet, analytical models for Seebeck effect coefficient (SB) and specific heat (Cph) are developed, which are found to be in good agreement with the experimental data. Using those analytical models, it is predicted that one can achieve a thermoelectric figure of merit (ZT) of ~ 0.62 at room temperature by adding isotopic impurities (C13 atoms) in a degenerate SLG. Such prediction shows the immense potential of graphene in waste-heat recovery applications. Those models for σ, κ, SB and Cph are further used to determine the time evolution of temperature distribution along suspended SLG sheet through a transient analysis of Joule-heating equation under the Thomson effect. The proposed methodology can be extended to analyze the graphene heat-spreader theory and interconnects and graphene based thermoelectrics.

Researcher : Rekha Verma (2013)

 Technology scaling beyond Moore’s law demands cutting-edge solutions of the gate length scaling in sub-10 nm regime for low power high speed operations. Recently SOI technology has received considerable attention, however manufacturable solutions in sub-10 nm technologies are not yet known for future nanoelectronics. Therefore, to continue scaling in sub-10 nm region, new one (1D) and two dimensional (2D) “nano-materials” and engineering are expected to keep its pace. However, significant challenges must be overcome for nano-material properties in carrier transport to be useful in future silicon nanotechnology. Thus, it is very important to understand and modulate their electronic band structure and transport properties for low power nanoelectronics applications. This thesis tries to provide solutions for some problems in this area. In recent times, one dimensional Silicon nanowire has emerged as a building block for the next generation nano-electronic devices as it can accommodate multiple gate transistor architecture with excellent electrostatic integrity. However as the experimental study of various energy band parameters at the nanoscale regime is extremely challenging, usually one relies on the atomic level simulations, the results of which are at par with the experimental observations. Two such parameters are the band gap and effective mass, which are of pioneer importance for the understanding of the current transport mechanism. Although there exists a large number of empirical relations of the band gap in relaxed Silicon nanowire, however there is a growing demand for the development of a physics based analytical model to standardize different energy band parameters which particularly demands its application in TCAD software for predicting different electrical characteristics of novel devices and its strained counterpart to increase the device characteristics significantly without changing the device architecture. The first part of this work reports the analytical modeling of energy band gap and electron transport effective mass of relaxed and strained Silicon nanowires in various crystallographic directions for future nanoelectronics. The technology scaling of gate length in beyond Moorefs law devices also demands the SOI body thickness, Tsi–> The investigations on ultrathin body materials also call for a need to explore new 2D materials with finite band gap and their various nanostructures for future nanoelectronic applications in order to replace conventional Silicon. In the third part of this report, we have investigated the electronic and dielectric properties of semiconducting layered Transition metal dichalcogenide meterials (MX2) (M = Mo, W; X = S, Se, Te) which has recently emerged as a promising alternative to Si as channel materials for CMOS devices. Five layered MX2 materials (except WTe2) in their 2D sheet and 1D nanoribbon forms are considered to study the real and imaginary band structure of those MX2 materials by atomistic simulations. Studying the complex dispersion properties, it is shown that all the five MX2 support direct BTBT in their monolayer sheet forms and offer an average ON current and subthreshold slope of 150 µA/µm and 4 mV/dec, respectively. However, only the MoTe2 support direct BTBT in its nanoribbon form, whereas the direct BTBT possibility in MoS2 and MoSe2 depends on the number of layers or applied uniaxial strain. WX2 nanoribbons are shown to be non-suitable for efficient TFET operation. Reasonably high tunneling current in these MX2 shows that these can take advantage over conventional Silicon in future tunnel field effect transistor applications.

Researcher : Ram Krishna Ghosh (2013)

Independent double gate (IDG) metal oxide semiconductor field effect transistor (MOSFET) has received considerable attention in recent years owing to its ability to modulate threshold voltage and transconductance dynamically. Due to the asymmetric nature of electrostatic, developing efficient compact models for such devices is a daunting task in comparison to the symmetric double gate transistor. The thesis tries to provide solutions for some problems in this area. The modeling of the long channel potential by solving the one-dimensional Poisson equation (PE) is the most fundamental step towards developing surface-potential-based core compact models for such transistors. Previous techniques used for solving the one-dimensional Poisson equation rigorously for the long channel asymmetric and independent double gate transistors result in potential models that involve multiple inter-coupled implicit equations. As these equations need to be solved self-consistently, such potential models are clearly inefficient for compact modeling. This work reports a different rigorous technique for solving the same Poisson equation by which one can obtain the potential profile of a generalized independent double gate transistor that involves a single implicit equation. The proposed Poisson solution is shown to be at-least five times computationally more efficient for circuit simulation than the previous solutions. Developing efficient models for terminal charges is another crucial step towards compact modeling. In this work we show the limitations of the traditional charge linearization techniques for modeling terminal charges of the IDG MOSFETs. We propose a new charge linearization technique in order to model the terminal charges and transcapacitances of the IDG MOSFETs. We report two different types of quasi-static large signal models for the long channel device. In the first type, the terminal charges are expressed as closed form functions of source and drain end inversion charge densities and found to be accurate when the potential distribution at source end of the channel is hyperbolic in nature. The second type, which is found to be accurate in all regimes of operations, is based on quadratic spline collocation technique and requires the input voltage equation to be solved two more times apart from the source and drain end. Proposed model has been successfully implemented in professional circuit simulator. Voltage controlled oscillators (VCOs) based on metal oxide semiconductor (MOS) varactors have become an integral part of RF communication circuits. An independently controlled double gate based MOS capacitor can bring out new functionalities, which could be interesting for RF circuit applications. For the first time, this work, explores the characteristics of MOS capacitor controlled by independent double gates by numerical simulation and analytical modeling for its possible use in RF circuit design as a varactor. By numerical simulation it is shown how the quasi-static and non-quasi-static characteristics of the first gate capacitance could be tuned by the second gate biases. Analytical solution of complete (considering both electron and hole concentration) Poisson equation (PE) is proposed. A new set of input voltage equations (IVEs) for independent double gate MOSFET are proposed by solving the governing bipolar Poisson equation rigorously. The proposed IVEs, involve the Legendre’s incomplete elliptic integral of the first kind andJacobian elliptic functions and are valid from accumulation to inversion regimes. As Legendre’s incomplete elliptic integral of first kind and Jacobian elliptic functions are computationally expensive, hence I also propose a semi-empirical solution using previous analytical solution of the PE for IDG MOS capacitor considering only electron/hole. Proposed models, which are valid from accumulation to inversion, are shown to have excellent agreement with numerical simulation for practical bias conditions.

Researcher : Pankaj Kumar Thakur (2013)

For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology scaling beyond 22nm node, it is clear that conventional bulk-MOSFET needs to be replaced by new device architectures, most promising being the Multiple-Gate MOSFETs MuGFET). Intel in mid 2011 announced the use of bulk Tri-Gate FinFETs in 22nm high volume logic process for its next-gen IvyBridge Microprocessor. It is expected that soon other semiconductor companies will also adopt the MuGFET devices. As like bulk- MOSFET, an accurate and physical compact model is important for MuGFET based circuit design. Compact modeling effort for MuGFET started in late nineties with planar double gate MOSFET (DGFET), as it is the simplest structure that one can conceive for MuGFET devices. The models so far proposed for DG MOSFETs are applicable for common gate symmetric DG (SDG) MOSFETs where both the gates have equal oxide thick- nesses. However, for practical devices at nanoscale regime, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. At the same time, Independently controlled DG (IDG) MOSFETs have gained tremendous attention owing to its ability to modulate threshold voltage and transconductance dynamically. Due to the asymmetric nature of the electrostatic, developing efficient compact models for asymmetric/independent DG MOSFET is a daunting task. In this thesis effort has been put to provide some solutions to this challenge. We propose simple surface-potential based compact terminal charge models, applicable for Asymmetric Double gate MOSFETs (ADG) in two configurations 1) Common-gate 2) Independent-gate. The charge model proposed for the common-gate ADG (CDG) MOSFET is seamless between the symmetric and asymmetric devices and utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and can be easily implemented in any circuit simulator and extendable to short-channel devices. The charge model proposed for independent ADG (IDG) MOSFET is based on a novel piecewise linearization technique of surface potential along the channel. We show that the conventional “charge linearization techniques that have been used over the years in advanced compact models for bulk and double-gate (DG) MOSFETs are accurate only when the channel is fully hyperbolic in nature or the effective gate voltages are same. For other bias conditions, it leads to significant error in terminal charge computation. We demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel for a particular bias condition actually dictates if the conventional charge linearization technique could be applied or not. We propose a piecewise linearization technique that segments the channel into multiple sections where in each section, the assumption of quasi-linear relationship between the surface potentials remains valid. The cumulative sum of the terminal charges obtained for each of these channel sections yield terminal charges of the IDG device. We next present our work on modeling the non-ideal scenarios like presence of body doping in CDG devices and the non-planar devices like Tri-gate FinFETs. For a fully depleted channel, a simple technique to include body doping term in our charge model for CDG devices, using a perturbation on the effective gate voltage and correction to the coupling factor, is proposed. We present our study on the possibility of mapping a non-planar Tri-gate FinFET onto a planar DG model. In this framework, we demon- strate that, except for the case of large or tall devices, the generic mapping parameters become bias-dependent and an accurate bias-independent model valid for geometries is not possible. An efficient and robust “Root Bracketing Method” based algorithm for computation of surface potential in IDG MOSFET, where the conventional Newton-Raphson based techniques are inefficient due to the presence of singularity and discontinuity in input voltage equations, is presented. In case of small asymmetry for a CDG devices, a simple physics based perturbation technique to compute the surface potential with computational complexity of the same order of an SDG device is presented next. All the models proposed show excellent agreement with numerical and Technology Computer-Aided Design (TCAD) simulations for all wide range of bias conditions and geometries. The models are implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.

Researcher : J. Srivatsava (2013)

Although scaling of CMOS (Complementary Metal Oxide Semiconductor) technology has been predicted to continue for another decade, novel technological solutions are required to overcome the fundamental limitations of the decananometer MOS transistors. Single Electron Transistor (SET) has attracted attention mainly because of its unique Coulomb blockade oscillations characteristics, ultra low power dissipation and nano-scale feature size. Despite the high potential, due to some intrinsic limitations (e.g., very low current drive) it will be very difficult for SET to compete head-to-head with CMOS’s large-scale infrastructure, proven design methodologies, and economic predictability. Nevertheless, the characteristics of SET and MOS transistors are quite complementary. SET advocates low-power consumption and new functionality (related to the Coulomb blockade oscillations), while CMOS has advantages like high-speed driving and voltage gain that can compensate the intrinsic drawbacks of SET. Therefore, although a complete replacement of CMOS by single-electronics is unlikely in the near future, it is also true that combining SET and CMOS one can bring out new functionalities, which are un-mirrored in pure CMOS technology. As the hybridization of CMOS and SET is gaining popularity, silicon SETs are appearing to be more promising than metallic SETs for their possible integration with CMOS. SETs are normally studied on the basis of the classical Orthodox Theory, where quantization of energy states in the island is completely ignored. Though this assumption greatly simplifies the physics involved, it is valid only when the SET is made of metallic island. As one cannot neglect the quantization of energy states in a semiconductive island, it is extremely important to study the effects of energy quantization on hybrid CMOS-SET integrated circuits. The main objective of this thesis is to understand energy quantization effects on SET by numerical simulations, develop simple analytical models that can capture the energy quantization effects, analyze the effects of energy quantization on SET logic inverter, and finally, develop a CAD framework for CMOS-SET co-simulation and to study the effect on energy quantization on hybrid circuits using that framework. In this work the widely accepted SIMON Monte Carlo (MC) simulator for single electron devices and circuits is used to study the effect of energy quantization. So far SIMON has been used to study SETs having metallic island. In this work, for the first time, we have shown how one can use SIMON to analyze SET island properties having discrete energy states. It is shown that energy quantization mainly changes the Coulomb Blockade region and drain current of SET devices and thus affects the noise margin, power dissipation, and the propagation delay of SET logic inverter. A new model for the noise margin of SET inverter is proposed, which includes the energy quantization term. Using the noise margin as a metric, the robustness of SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termed as “Quantization Threshold”) that an SET inverter logic circuit can withstand before its noise margin falls below a specified tolerance level. It is found that SET inverter designed with CT : CG = 0.366 (where CT and CG are tunnel junction and gate capacitances respectively) offers maximum robustness against energy quantization. Then the effects of energy quantization are studied for Current biased SET (CBS), which is an integral part of almost all hybrid CMOS-SET circuits. It is demonstrated that energy quantization has no impact on the gain of the CBS characteristics though it changes the output voltage levels and oscillation periodicity. The effects of energy quantization are further studied for two circuits: Negative Differential Resistance (NDR) and Neurone Cell, which use CBS. A new model for the conductance of NDR characteristics is also formulated that includes the energy quantization term. A novel CAD framework is then developed for CMOS-SET co-simulation, which uses MC simulator for SET devices along with conventional SPICE. Using this framework, the effects of energy quantization are studied for some hybrid circuits, namely, SETMOS, multiband voltage filter, and multiple valued logic circuits. It is found that energy quantization degrades the performance of hybrid circuit, which could be compensated by properly tuning the bias current of SET devices. Though this study is primarily done by exhaustive MC simulation, effort has also been put to develop first order compact model for SET that includes energy quantization effects. Finally it is demonstrated that one can predict the SET behavior under energy quantization with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

Researcher : Surya Shankar Dan (2009)