E1:201 Hardware Acceleration and Optimization for Machine Learning

Term : January – April 2020
Instructor : Dr. Chetan Singh Thakur
Class Schedule :  Lecture : Tue,Thu 9-10 AM, Lab: Fri 2-5 PM.
TA : Abhishek Nair (Email : abhisheknair@iisc.ac.in)
Credits :  2:1

Course Summary:
Overview of machine learning hardware systems, motivation and trends, fundamentals of digital hardware – FPGA, power and speed estimation, accelerating linear algebra, machine learning system concepts – (SVM and Deep Learning Neural Networks), feature extraction (PCA, filtering), inference engine, matrix vector multiplication (sparsity), non-linearity and pooling, resolution-performance trade-off, training optimization engines (cost function, regularization), online and stochastic training, forward-backward propagation, emerging hardware architectures, memristor based designs, spiking architectures

Basics of linear algebra, calculus, probability, basic knowledge of C/Python.
Note: No prior experience in FPGA or HDL languages (Verilog/VHDL) are required, as the hardware implementation will use high level synthesis framework from Xilinx.

Current literature

First Day of Class :  14th January 2020
Midterm :  TBA
Project Presentations : TBA
Final Exam : TBA

Lecture Notes and Handouts:

Vivado HLS tool and Vivado design suite:
The simulations and implementation of the IPs developed onto FPGA for this class will require the use of Vivado Design suite which includes Vivado HLS tool. Tutorials will be conducted in the Lab Timings for students to get started on the tools for developing the IPs.
Students are urged to install the Vivado Design tool and get familiar with the Vivado HLS environment. We will be using PYNQ FPGA boards for implementation.

Attendance and Conduct in Class:
Students are expected to attend classes and be attentive and responsive to all class discussions. It is the students responsibility to get notes and handouts for any missed class.

The grades will be assigned according to the following credit table.
Class participation (TBA% ), Midterm (TBA%),  Project  (TBA%), Final Exam (TBA%)

As part of the project, a group of 2 students will design systems using software algorithms (ML, Neuromorphic or Neural Networks). The final project presentation should involve clear distinctions of the software algorithms ported as IPs using HLS and their integration with the larger system as a product using Vivado Design Suite. Finally implementing these on PYNQ FPGA board for prototyping. Grading will be based on the project presentation, report, simulation and prototyping of the system.