Term : August – December 2019
Instructor : Chetan Singh Thakur
Class Schedule : Mon-Wed : 10-11 AM : DESE Auditorium , Lab : Fri : 5PM
TA : Pratik Kumar (Email : firstname.lastname@example.org),
Credits : 2:1
Introduction to MOS transistor theory, Circuit characterization & simulation, theory of logical effort,interconnect design and analysis combinational circuit design, sequential circuit design. Design methodology & tools, testing & verification, datapath subsystems, array subsystems, power and clock distribution, introduction to packaging.
- N. W este and D. Harris, CMOS VLSI Design. A Circuits and Systems Perspective, Addison Wesley, 2005
- J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits
- Current literature
First Day of Class : 5th Aug 2019.
Assignment 1 Deadline : 19th Oct 2019, 11:59 PM.
Midterm Project Presentation : 25th-26th Oct 2019.
Assignment 2 Deadline : 17th Nov 2019, 11:59.
Final Project Presentations : 27th-28th Nov 2019.
Final Exam : 3rd Dec 2019.
Lecture Slides and Lab notes:
- Introduction to VLSI
- Characteristics of MOSFET
- Sequential Design
- ASIC Design
- Analog Subthreshold
Lab 1. Introduction to Analog and ASIC design tools and setup
Lab 2. Analog tools hands on
Lab 3. Verilog tutorial
Lab 4. ASIC Flow
Lab 5. Advanced Mixed Signal Flow
The projects will be implemented using standard ASIC flow provided in Cadence.
Attendance and Conduct in Class:
Students are expected to attend classes and be attentive and responsive to all class discussions. It is the students responsibility to get notes and handouts for any missed class.
The grades will be assigned according to the following credit table.
Assignments (15% ), Midterm (20%), Project (30%), Final Exam (35%)
Students will be grouped for the projects. The aim is to understand the problem and provide a hardware implementation in verilog. This verilog code needs to be converted to ASIC using Cadence tool.