Dr. Harald Gossner Harald Gossner is Senior Principal Engineer at Intel, where he oversees the development of robust mobile systems. Since February 2011 he is the technical lead of ESD and LU protection design of Intel’s mobile ICs and in charge of Intel’s systemlevel ESD protection methodology.  Prior to his engagement with Intel he has worked on the development of ESD protection with Siemens and Infineon Technologies for 15 years. In 2006 he has cofounded the Industry Council on ESD Target level and is co-chair of the committee representing more the 50 leading companies in the field of electronics and semiconductors. Since 2012 he is also member of the board of directors of ESD Association. Harald Gossner has authored and co-authored more than 130 technical papers and two books in the field of ESD and device physics. The book on ‘Advanced Simulation Methods for ESD Protection Development’ was published in 2003, and the monograph on ‘System Level ESD Co-Design’ in 2015, which introduces the novel concept of IC and PCB ESD protection co-design. He holds  more than 80 patents on the topics of ESD protection, novel devices and verification tools. He received the best paper awards of EOSESD Symposium in 2005, 2012 and 2017 and has been the recipient of the 2015 Outstanding Contribution Award of ESD Association.

Dr. Charvaka Duvvury was a Texas Instruments fellow while he worked in the Silicon Technology Development group at TI.  He received his PhD in engineering science from the University of Toledo and afterwards worked as a post-doctoral fellow in Physics at the University of Alberta. His experience at Texas Instruments spanned for 35 years in semiconductor device physics with pioneering development work in ESD design. He has also mentored PhD students at several leading US universities on their investigations in ESD research and received Outstanding Industry Mentor Award twice from the SRC. Charvaka has published over 150 papers in technical journals and conferences and holds more than US 75 patents. He co-authored and contributed to 5 books on the subject. He is a recipient of the IEEE Electron Devices Society’s Education Award and Outstanding Contributions Award from the EOS/ESD Symposium. Charvaka has been serving on Board of Directors of the ESD Association (ESDA) since 1997 promoting ESD education and research at academic institutes. He is co-founder and co-chair of the Industry Council on ESD since 2006. During 2015 he became a co-founder of the iT2 Technologies that utilizes software engine and machine learning for rapid ESD data analysis. Charvaka is also Fellow of the IEEE.

Dr.  Gianluca Boselli completed his master in EE at the University of Parma (Italy, 1996) and his PhD at the University of Twente (The Netherlands, 2001), where he worked on high current phenomena in CMOS  technologies. In 2001, he joined Texas Instruments, Inc., Dallas, Texas, where he focused on ESD and latch-up development for advanced CMOS technologies, with particular emphasis on process and modeling aspects. In 2009 he was promoted corporate ESD Design and Development Manager to support the entire Texas Instruments portfolio. Since 2014, his responsibilities extended into compact modeling, where he is now compact modeling corporate manager, with responsibility to deliver compact models and simulation infrastructures to Texas Instruments design community.He authored several papers in the area of ESD and latch-up. He presented his work at major conferences, including EOS/ESD Symposium, IEDM, and IRPS. He has also presented many invited tutorials and papers at various conferences, including EOS/ESD Symposium, IRPS, IEDM, ESREF, IEW, and RCJ. Dr. Boselli has been the recipient of the best paper award on behalf of Microelectronics Reliability Journal in 2000. He received the best paper award at the EOS/ESD Symposium 2002. He also received the Outstanding Symposium award at the EOS/ESD Symposium in 2002, 2006, and 2010. Dr. Boselli served multiple times as sub-committee chair for technical program committees (TPC) of EOS/ESD Symposium, IEDM, IRPS, IEW, and ESREF. He served as moderator and panelist in many workshops in ESD and latch-up area.  Dr. Boselli has served as TPC chair at the EOS/ESD Symposium 2006, vice-general chair at the EOS/ESD Symposium 2007, and general chair at the EOS/ESD Symposium 2008. He is currently a member of the board of directors of EOS/ESD Association, Inc.; where he is the President Emeritus. He is the recipient to ESDA Outstanding Contribution Award. Dr. Boselli is an IEEE senior member and holds over thirty patents with several pending. Dr. Boselli serves in the editorial board of the IEEE Transactions on Device and Materials Reliability (T-DMR).

Dr. Theo Smedes holds an Msc and Ph.D in device modeling aspects from the Eindoven University of Technology. He spent the next four years at the Delft University of Technology on the development of circuit extraction software for substrate coupling analysis. Theo joined Philips Semiconductors in 1995 where he began work on statistical circuit simulations. In 1999 he became involved with ESD, servicing the design teams within the company and attended the 1999 symposium where he started his ESD education. In 2006 Philips Semiconductors became NXP Semiconductors where Theo is still working in the field of ESD and is active representing NXP in the industry council.