E0 217: Efficient and Secure Digital Circuits and Systems (August 2023)
Instructor: Utsav Banerjee
Lecture Timings: Monday & Wednesday 11am-12pm
Lab / Tutorial Timings: Thursday 5:30pm
Location: First Floor Auditorium (DESE 201)
Teaching Assistants: Niladri Podder, Ashritha Mula, Vaishali Kumari, Aniket Banerjee, Dhrupadi Das
Course Description: This is an introductory graduate-level course on the design and analysis of digital circuits and systems with an emphasis on efficient and secure implementation aspects. This course will cover co-optimization of circuits, architectures and algorithms for the design of application-specific digital systems with different power, performance, area and energy-efficiency requirements. Techniques for securing such systems using efficient implementation of encryption, authentication and side-channel countermeasures will also be covered. Various digital circuit and system concepts will be introduced using a combination of lectures, homework assignments and a project.
Prerequisites: Basic understanding of digital electronic circuits.
Credits: 2:1
Syllabus:
▶ Circuits: overview of CMOS digital circuit design, logic gates, combinational and sequential logic, finite state machines, arithmetic circuits, memories, timing considerations, power consumption
▶ Systems: overview of computer architecture, instruction set, hardware-software interaction, micro-controllers, hardware acceleration, FPGA and ASIC design
▶ Efficiency: gate-level optimization for power-performance-area, low-power versus energy-efficient implementation, pipelining, multi-level memories and caches
▶ Security: introduction to cryptography and hardware security, implementation of multi-precision modular arithmetic, side-channel attacks and countermeasures
References:
1. J. M. Rabaey, A. P. Chandrakasan and B. Nikolic, “Digital Integrated Circuits: A Design Perspective”.
2. N. H. E. Weste and D. M. Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”.
3. D. M. Harris and S. L. Harris, “Digital Design and Computer Architecture”.
4. M. M. Mano and M. D. Ciletti, “Digital Design”.
5. Journal / Magazine Articles and Conference Papers.
Grading: The grade will be based on ten problem sets, two mid term exams, a final exam and a project. Assignments must be submitted by 11:59pm on the day they are due. Late submissions will not be accepted for grading. The final grade will be calculated approximately based on the following weights: Problem Sets (10%), Mid Term Exam 1 (10%), Mid Term Exam 2 (15%), Project (20%) and Final Exam (45%).
Problem Sets: The problem sets will contain questions based on numerical calculations as well as circuit / system / software simulations. Various open-source tools will be used for the simulation tasks and their setup instructions will be shared during the lab tutorials.
Project: There will be a set of well-defined projects to choose from and conduct in groups of 2-3. These projects will provide hands-on experience with the analysis and implementation aspects of digital circuits and systems.
Course Materials: Lecture slides, tutorials, simulation models, projects and additional readings will be shared using a Microsoft Teams group which will be accessible only to registered students.
Schedule:
Reference Textbook Chapter Readings |
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Lecture | Topic | Ref. 1 |
Ref. 2 |
Ref. 3 |
Ref. 4 |
1 | Introduction and Course Overview | 1 & 2 |
1 | ||
2 | MOS Transistor | 3 | 2 | ||
3 | CMOS Inverter (Part 1) | 5 |
2 | ||
4 | CMOS Inverter (Part 2) | 5 | 2 | ||
5 | Combinational Logic |
6 |
9 | 1 & 2 |
1 – 4 |
6 | Sequential Logic |
7 |
10 | 3 |
5 & 6 |
7 | Timing Considerations |
7 & 10 |
4 & 10 |
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8 | Power Consumption | 6 | 5 & 9 |
||
9 | Arithmetic Circuits (Part 1) | 11 | 11 | 5 |
|
10 | Arithmetic Circuits (Part 2) | 11 | 11 | 5 | |
11 | Memories | 12 | 12 | 5 |
7 |
12 | Design Trade-Offs (Part 1) | ||||
13 | Design Trade-Offs (Part 2) | ||||
14 | Design Trade-Offs (Part 3) | ||||
15 | FPGA and ASIC | 8 | 14 |
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16 | Processor Architecture (Part 1) | 6 & 7 |
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17 | Processor Architecture (Part 2) | 6 & 7 |
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18 | Processor Architecture (Part 3) | 6 & 7 |
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19 | Processor Architecture (Part 4) | 6 & 7 |
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20 | Hardware Accelerators |
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21 | Cryptography and Hardware Security | ||||
22 | Cryptographic Hardware Implementation | ||||
23 | Side-Channel Analysis |
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24 |
Hardware Security Primitives | ||||
25 |
Advanced Topics |