E0 297: Cryptographic Hardware Accelerators (August 2026)

 

Instructor: Utsav Banerjee

Lecture Timings: Monday & Wednesday 11:30am-12:30pm

Lab / Tutorial Timings: Tuesday 2:30pm

Location: First Floor Auditorium (ESE 201)

Teaching Assistants: TBD

 

Course Description: This is an advanced graduate-level course on the design and implementation of cryptographic hardware accelerators. This course will cover co-design of circuits, architectures and algorithms for cryptography with different power, performance, area, energy efficiency and security requirements. Various state-of-the-art implementation techniques and design trade-offs will be introduced using a combination of lectures, design assignments and a final project.

Prerequisites: Both E0 284 (Digital VLSI Circuits) and E3 231 (Digital System Design with FPGAs).

Credits: 2:1

Syllabus: Introduction to Symmetric Key and Public Key Cryptography, Advanced Encryption Standard (AES), Secure Hash Algorithm (SHA), Light-Weight Cryptography, Multi-Precision Integer Modular Arithmetic, Rivest-Shamir-Adleman (RSA), Elliptic Curve Cryptography (ECC), Circuit-Algorithm-Architecture Co-Optimizations, Efficient Hardware Implementations, Timing and Power Side-Channel Analysis, Algorithm-Level and Architecture-Level Side-Channel Countermeasures.

References: Journal Articles, Conference Papers, Preprints and Cryptography Standards.

 

Grading: The grade will be based on three design assignments, two quizzes, a paper review, a final project and class participation. Assignments must be submitted by 11:59pm on the day they are due. Late submissions will not be accepted for grading. The final grade will be calculated tentatively based on the following weights: Class Participation (10%), Paper Review Assignment (10%), Quiz 1 (10%), Quiz 2 (20%), Design Assignments (15%) and Final Project (35%). This course will have no final exam.

Design Assignments: There will be 3 well-defined RTL design assignments to be completed individually using prescribed open-source digital simulation / synthesis tools. These will provide hands-on experience with the design, analysis and implementation aspects of cryptographic hardware acceleration. The design assignments for this term are as follows: 1. AES-256 Block Cipher, 2. Keccak-f[1600] Permutation, and 3. Modular Exponentiation for 15360-bit RSA.

Course Materials: Lecture slides, tutorials, assignments, projects and reading materials will be shared using a Microsoft Teams group which will be accessible only to registered students.

 

Schedule:

Lecture	Topic	References
1	Introduction and Course Overview
2	Basics of Cryptographic Protocols
3	Symmetric Key Cryptography (Part 1)
4	Symmetric Key Cryptography (Part 2)
5	Implementation of AES (Part 1)	NIST FIPS 197
6	Implementation of AES (Part 2)	NIST SP 800-38A, NIST SP 800-38D
7	Implementation of SHA2 and SHA3	NIST FIPS 180-4, NIST FIPS 202
8	Implementation of ASCON	NIST SP 800-232
9	Lightweight Ciphers	KATAN, SIMON / SPECK, PRESENT, Trivium
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