Publications

Journal

- - S. Taneja, Viveka Konandur Rajanna and M. Alioto “Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security, in IEEE Journal of Solid-State Circuits (JSSC), vol. 57, no. 1, pp. 153-166, Jan. 2022. JSSC’22
  - Viveka Konandur Rajanna and Massimo Alioto, “On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications”, in IEEE Journal of Solid-State Circuits (JSSC), vol. 56, no. 11, pp. 3533-3543, Nov. 2021. JSSC’21
  - Viveka Konandur Rajanna and Bharadwaj Amrutur, “A Variation Tolerant Replica Based Reference Generation Technique for Single-Ended Sensing in Wide Voltage Range SRAMs”, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1663-1674, May 2016. TVLSI’16

Conference

- - A. Gupta, J. Vohra, Viveka Konandur Rajanna, M. Alioto, “122.7 TOPS/W Stdcell-Based DNN Accelerator Based on Transition Density Data Representation, Clock-Less MAC Operation, Pseudo-Sparsity Exploitation in 40 nm,” accepted to VLSI Symposium 2024, Honolulu (USA), June 2024. VLSI’24
  - K A Ahmed*, R Yang*, P Salamani, Viveka Konandur Rajanna, and M. Alioto “Single-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 μW Peak Power for Purely-Harvested Green Systems”, ESSCIRC 2023 – IEEE 49th European Solid-State Circuits Conference (ESSCIRC), (accepted, in press). ESSCIRC’23
  - A. Gupta, S. Kumar, Viveka Konandur Rajanna, S. Taneja, M. Alioto, “Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm,” in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023. VLSI’23
  - J. Basu, Sachin Taneja, Viveka Konandur Rajanna, T. Wang, M. Alioto, “ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm,” in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023. VLSI’23
  - Viveka Konandur Rajanna*, H. Singh Raghav*, T. Wang and M. Alioto, “Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks,” 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2022, pp. 144-145. VLSI’22
  - A. Gupta, Viveka Konandur Rajanna, T. Singh, S. Jain, O. Aiello, P. Crovetti and M. Alioto, “DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm ² in 40nm,” 2022 IEEE Custom Integrated Circuits Conference (CICC), Newport Beach, CA, USA, 2022, pp. 1-2. CICC’22
  - Viveka Konandur Rajanna, S. Taneja and M. Alioto, “SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm² and 749-1,459 TOPS/W in 28nm,” ESSCIRC 2021 – IEEE 47th European Solid State Circuits Conference (ESSCIRC), Grenoble, France, 2021, pp. 127-130. ESSCIRC’21
  - P. Agarwal*, Viveka Konandur Rajanna*, T. W. Da, B. C. K. Tee and M. Alioto “Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm2 per Receptor for Scaling to Human-Like Tactile Sensing Density, 2021 Symposium on VLSI Circuits, pp. 1-2. VLSI’21
  - S. Taneja, Viveka Konandur Rajanna and M. Alioto “36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security, 2021 IEEE International Solid-State Circuits Conference (ISSCC), pp. 498-500. ISSCC’21
  - Viveka Konandur Rajanna and M. Alioto “Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications”, 2019 IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4. CICC’19
  - Viveka Konandur Rajanna and Bharadwaj Amrutur, “Presentation at the 2015 ISSCC Student Research Preview session.ISSCC’15, SRP
  - K.R.Viveka and Bharadwaj Amrutur “Energy Efficient Memory Decoder Design for Ultra-low Voltage Systems”, Proceedings of the IEEE VLSI Design 2014 conference, pp. 145-149, Jan 2014. VLSID’14
  - K.R.Viveka and Bharadwaj Amrutur “Digitally controlled variation tolerant timing generation technique for SRAM sense amplifiers”, Proceedings of the IEEE Asia Symposium on Quality Electronic Design (ASQED), 2013, pp. 233 – 239, Aug 2013.ASQED’13
  - K.R.Viveka, Abhilasha Kawle and Bharadwaj Amrutur “Low Power Pipelined TCAM Employing Mismatch Dependent Power Allocation Technique, Proceedings of the IEEE VLSI Design 2007 conference, pp. 638-643, Jan 2007. VLSID’07
  - K.R.Viveka, Ramgopal S, Praveen N, Rajanna K and Nayak M.M “Pressure Sensor Based Tsunami Detection System: A Laboratory Study”, Proceedings of IEEE sensors 2006 conference, pp. 1392-1394, Oct. 2006. SENSORS’06
  * equal contribution

Press

Network on Chip with quintupled energy efficiency for artificial intelligence applications

National University of Singapore (NUS) press release