Current Projects

Vinay Kumar Nalabolu
AXI Interconnect Design

Mayank Sharma
Accelerator for LoFreq Genome Variant Calling

Abhikriti Maurya
Processor Synthesis using HLS

Kongara Sai Ram, Chunarkar Shreyash Shailendra
64-bit RISC-V ASIC

Yerukala Sai Sharath
SLAM Accelerator on FPGA

Sai Charan Katakam, Sri Sai Nomula
Hardware Accelerator of BWFA-MEM2
on Alveo U50 using HLS

Toms Jiji Vargehese, Sanidhya Saxena
A 32-bit RISC -V ASIC

Previous Projects (ESE Students)

1990 – 92	Data Multiplexer	Mohan M S S
1991 – 93	High performance Data Acquisition system	D Thirugnana Murthy
1992 – 94		Srirama S
1993 – 95	Network Protocol Analyzer	Rajesh Joshi, Parvati Uma
1994 – 96	SERCOS Communication Controller for DSP based drives	Milind Vasant Rao Pande	CIMTRIX Systems
1998 – 00	V5.2 Access Network	S Jairam, Divya Tripathi	MITEL
1999 – 01	Integrated Access Device and gateway	Prashant Jain Arati Godbole	ZARLINK

2000 – 02	Remote Bluetooth LAN Access point	Sudheer S S, Tarun Katara	Impulsesoft Pvt. Ltd.
2001 – 03	H.323 based Video conferencing Terminal	Nidhish Gaur, Rajiv Kaushal	TI
2003 – 05	Cryptographic Ip for NIOS Processor	Ajit Oke, Pankaj Sharma	Altera
2004 – 06	Firewall IP for FPGA	Piyush Khanwalkar, Shantanu Nalage	Xilinx
2004 – 06	Floating point Unit for Nios II Processor	Desai Kunal Mukesh, J. Karthik Ramkumar	Altera
2005 – 07	Firewall IP for FPGA	Arun R Gajanan Jedhe	Xilinx
2005 – 07	CESOP Processor	Venumadhav Bhagavatula, Yaswanth Chowdary S	Zarlink

2006 – 08	H.264 Decoder Implementation (Intra-predictor)	Jimit Shah, Raghunandan K S	Xilinx
2006 – 08	Network Intrusion Detection System	Tejasvi Anand, Yagnesh Waghela	Xilinx
2007 – 09	Network Intrusion Detection System II	Deepak. K. G, Robinson Reyna	Xilinx
2007 – 09	H.264 Decoder Inter IP Implementation On FPGA	Hitesh Kumar Gupta, Mrinmay Dutta	Xilinx
2008 – 10	Hardware Accelerator for Pair Wise Sequence Alignment	Raghavendra Adiga, Gandhi Arpit Ashokkumar	Xilinx
2008 – 10	Network Access Traffic Manager	Poovaiah M P, Sushanth Kini	Xilinx
2009 – 11	Hardware Accelerator for Multiple Sequence Alignment of Proteins/DNA	Amit Mishra, Nidhi Sinha,	Xilinx
2009 – 11	Transparent FPGA based Device for SQL DDoS Mitigation	Karthikeyan P, Srijith Haridas	Xilinx
2010 – 12	Hardware Accelerator for Support Vector Machine Learning	Arun Ajith S, Siva Satyendra Sahoo	Xilinx
2010 – 12	Hardware Accelerator for Multiple Sequence Alignment – II	Abhra Bagchi, Sumanta Pal	Xilinx

2011 – 13	Hardware Accelerator for Linear Solvers	Maulik Gandhi, Anand Devi
2011 – 13	Hardware Accelerator for Support Vector Machines	Sriram V, Alap Patel
2012 – 14	Hardware Accelerator for Probabilistic Load Flow Analysis	Himanshu Varshney, Chaitanya N S
2012 – 14	Accelerator for Short Read Alignment	Anish G S, Akash P
2013 – 15	GPU-Based Accelerator for Short Read Alignment	Rajib Lochan Swain, Manjunath Karikatti
2013 – 15	Hardware Accelerator for Support Vector Machines	Abhishek Das, Kalagatla Jayanth Kumar
2014 – 16	FPGA based coprocessor for Convolutional Neural Network Classification	Shah Nimish Shirish, Chaudhari Paragkumar
2014 – 16	Processor Design for Flight Control Computer	Kavya Sharat, Sumeet Bandishte
2014 – 16	Flow Control for Onboard Solid State Recorder	Siddhartha B Rai, Srinidhi M S
2015 – 17	FPGA based Reconfigurable Coprocessor for Deep Convolutional Neural Network Training	Sachin S, Sajna Remi Clere
2015 – 17	A RISC-V ISA Compatible Processor IP for SoC	Suseela Budi, Pradeep Gupta

2016 – 18	Run-Time Reconfigurable Co-Processor for Classification and Training of Binary Weighted CNN	S Krishna Chitanya, Jaynath K
2016 – 18	A RISC-V ISA Compatible Processor IP for SoC	Akshay Birari, Piyush Birla
2016 – 18	A High Throughput Kernel Coprocessor for Support Vector Machine	Desai Jagannath Vishnuteja
2017 – 19	Hardware Accelerator for Capsule Network based Deep Reinforcement Learning	Dola Ram Suraj Panwar
2017 – 19	High Throughput Hardware for Online Learning	Devi A Ashin Antony
2017 – 19	Superscalar RISC-V CPU	Gokulan T Akshay Muraleedharan
2018 – 20	FPGA Based Hardware Accelerator for Long Short-Term Memory Recurrent Neural Networks	Faruq Mulla S Gojri Parameswar Sampath
2018 – 20	Out of Order Superscalar 64-bit RISC-V CPU	Ronit Vijaybhai Patel Vishal Kumar
2018 – 20	Hardware Accelerated RNA Sequence Alignment using FPGA	Syam Krishnan C R
2019 – 21	Linux Compatible 64-bit Out of Order Superscalar RISC-V Processor	Anuj Phegade Deepshikha Gusain
2019 – 21	Runtime reconfigurable Accelerator for Convolutional Neural Network for Reinforcement learning	Arpit Rastogi Sai Vamshi Kandukuri

2020 – 22	Multi-core Out of Order 64-bit Superscalar RISC-V Processor	Sajin S, Shubam Sunil Garag
2020 – 22	Remote Lab Control and Monitoring Platform	Animesh Jain, Kalyan Kumar Prusty
2020 – 22	Hardware accelerator for Short Read Alignment using FPGA	Bindu P, Riya Aron
2021 – 23	Multi-core Out of Order 64-bit Superscalar RISC-V Processor	Manish Kumar,Shubham Yadav
2021 – 23	Remote Lab Control and Monitoring Platform	Akshit Agiwal, Piyush Songara
2021 – 23	FPGA based Pairwise Wavefront Sequence Alignment	Ajay SPraveen V
2022 – 24	32-bit RISC-V Processor on FPGA with RTOS	Amol Madhavrao Ibitwar
2022 – 24	Hardware Arbitrary Precision Floating Point operationson FPGA	Arimardan Rai
2022 – 24	32-bit RISC-V ASIC Design using RTL and HLS	Akkaluru Divya, Katasani Varsha

Previous Projects (Micro-Electronics Students)

2001 – 03	CPU for Cryptography	Ajayan K R
2001 – 03	Implementation of division algorithms	Vinod Kumar
2002 – 04	IEEE 802.11 MAC Chip	Agnish Jain Hemant Parate
2003 – 05	FPGA Implementation of Digital Beamformer based on QR decomposition RLS algorithm using CORDI Arithmetic	Paramanand Jena Rakesh Oza
2004 – 06	FPGA Implementation of Traffic Shaper	C Arun Prasath B Prashanth Kumar
2005 – 07	Implementing Elliptic Curve Cryptography on FPGA	P Sajjan Raj Jain M. Rajesh Kumar
2006 – 08	Dynamically Reconfigurable Regular Expression Matching Architecture	Divyasree J Rajashekar H
2007 – 09	Flow Control Scheme for Network-on-Chip	Vrishali Vijay Nimbalkar
2007 – 09	Runtime Partial Reconfiguration of FPGA	Jalpa Shah
2008 – 10	An Architecture for a Flexible Run Time Reconfigurable FPGA	Binoy M
2008 – 10	Hardware Accelerator for DNA Sequence Alignment on FPGA	Hari Banerji
2009 – 11	Counting Bloom Filter	Puneet Aseri
2009 – 11	Design of Fault Tolerant FSM	Siva Sekhar Y
2010 – 11		Ashwal Vinay Toppo

2016 – 18	Coprocessor for SNAP Aligner	Jaison Varghese
2018 – 20	Hardware Accelerator for Restricted Boltzmann Machine	Shantam Srivastava
2019 – 21	A Softcore RISC-V Vector Processor for Edge-AI	Naveen Chander V
2019 – 21	Implementation of CNN on FPGA using FFT	Tejas Oturkar
2019 – 21	Hardware Accelerator for CNN based Deep Reinforcement Learning	Subham Agarwal

2020 – 22	High throughput Matrix Multiplication Implementation on FPGA	Yashwanth Kumar Kancharla
2020 – 22	Resource Efficient TCAM Implementation using SRAM	Madhu Ennampelli
2020 – 22	RISC-V for AI Applications	Katakam V N Manikanta Bhargav
2020 – 22	Hardware Accelerator for Particle Transport Simulations	Nagendranaik Ramavath Suraj Panwar
2021 – 23	RISC-V Out Of Order Vector Processor for ML inference engines	Jadiram Sai Charan
2021 – 23	Design and Implementation of a Posit Arithmetic Unit for High Performance Computing Systems	Sadhu Sai Ram
2021 – 23	Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment	Naresh Vankadavath
2021 – 23	Hardware Accelerator for Low Power Image Generation using HLS	Bhanu Prasad A
2022 – 24	Vector extension support for 64-bit RISC-V processor	Madepalli Govind,Teli Nikhil Yashwant
2022 – 24	AXI Interconnect IP Design	M Venkata Narayana Sai Maanas
2022 – 24	RISC-V Vector Extension for Cryptography	Tatavarthi Venkatanagaanjani S S Saisandeep