Reconfigurable Computing Lab
Areas of Work
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Computer Architecture
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Accelerators for High-performance computing in Computer Networks, Bioinformatics, Machine Learning, etc.
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Hardware Accelerator for SVM
![MicrosoftTeams-image (8)](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2021/09/MicrosoftTeams-image-8-scaled.jpg)
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Coprocessors for SVM, CNN, LSTM, RNN
![MicrosoftTeams-image](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2021/09/MicrosoftTeams-image-scaled.jpg)
![InkedKV RC Lab 2021-18_LI](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2021/09/InkedKV-RC-Lab-2021-18_LI-scaled.jpg)
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Scalar, Superscalar RISC-V Processors
![RISC_1](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/RISC_1.png)
![RISC_2](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/RISC_2.png)
![RISC_4](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/RISC_4.png)
![RISC_3](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/RISC_3.png)
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RISC-V Vector Machine
![SLVU_1](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/SLVU_1.png)
![SLVU_4](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/SLVU_4.png)
![SLVU_3](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/SLVU_3.png)
![SLVU_5](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/SLVU_5.png)
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Remote Lab Control and Monitoring Platform
![Remote_lab_2](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/Remote_lab_2.png)
![Remote_lab_1](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/Remote_lab_1.png)
![Remote_lab_3](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/Remote_lab_3.png)
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Hardware Accelerator for Short Read Alignment
![HASL_1](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/HASL_1.png)
![HASL_2](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/HASL_2.png)
![HASL_3](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/HASL_3.png)
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Resource Efficient implementation of Ternary Content Addressable Memories
![TCA_memories_1](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/TCA_memories_1.png)
![TCA_memories_3](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/TCA_memories_3.png)
![TCA_memories_2](http://labs.dese.iisc.ac.in/rclab/wp-content/uploads/sites/19/2022/08/TCA_memories_2.png)