Kuruvilla Varghese is a Chief Research Scientist at the Department of Electronic Systems Engineering (DESE, formerly CEDT), Indian Institute of Science, Bangalore. He is working at DESE since 1989. His main research interests are in Digital VLSI Systems and Computer Networks. Presently he is working on High performance accelerators for Machine Learning, Bioinformatics, and Networking using Field Programmable Gate Arrays (FPGA) in Reconfigurable Computing Lab at DESE.

Expertise

Digital Systems, VLSI, High Performance Accelerators, Computer Networks

Address and contact details

Department of Electronic Systems Engineering (DESE),
Indian Institute of Science (IISc), Bangalore 560 012. India.
Tel: + 91 80 2293 3092. Email: kuru@iisc.ac.in.

Akhila is pursuing M Tech (Res) in Electronics System Engineering (2024-2027). She received her Bachelor of Engineering in Electronics and Communication Engineering from National Institute of Technology Andhra Pradesh, Tadepalligudem in 2024. She is currently working on “Hardware Accelerator for BiWFA using HLS”.

Email: akhilac@iisc.ac.in

Deepa Ahuja is pursuing MTech in Electronic Systems Engineering (2024-2026). She completed her BTech in Electronics & Communication Engineering from Jabalpur Engineering College. She is currently working on the project “32-bit RISC-V ASIC Implementation”

Email: deepaahuja@iisc.ac.in

Hariom Chouhan is currently pursuing his M.Tech in Electronic Systems Engineering (2024–2026). He completed his B.Tech in Electronics and Communication Engineering from University Institute of Technology, RGPV, Bhopal, Madhya Pradesh in 2024. His academic interests include Digital VLSI Design, Computer Architecture, and Digital Systems Design. He is currently working on a project “32-bit RISC-V ASIC Implementation”, focusing on the design, verification, and hardware realization of a custom RISC-V processor.

Email: chariom@iisc.ac.in

Mutum Rajesh Meitei is currently pursuing his M.Tech in the Electronic Systems Engineering(2024-2026). He holds a B.Tech degree from NIT Manipur in 2024. His areas of interest include Digital VLSI, Digital System Design, and Embedded Systems. As part of his academic project, he is working on the implementation of a 32-bit RISC-V processor debug hardware module, with a focus on spec-compliant modular design and a simulation-driven development approach, and plans to expand the work toward ASIC design.

Email: rajeshmutum@iisc.ac.in

Rakesh Andavarapu is currently pursuing his M.Tech in Microelectronics and VLSI Design (2024–2026). He completed his B.Tech in Electronics and Communication Engineering from MVGR College of Engineering, Andhra Pradesh, in 2024. His areas of interest include Digital VLSI Design, Digital System Design, and Computer Architecture. He is presently working on the design and development of a “64-bit RISC-V ASIC” as part of his academic and research pursuits.

Email: rakesha@iisc.ac.in

Sudipta Das is currently pursuing his M.Tech in Microelectronics and VLSI Design (2024–2026). He completed his B.Tech in Electronics and Communication Engineering(ECE) from Jalpaiguri Government Engineering College, West Bengal. His areas of academic interest include Digital Systems Design, Digital VLSI Design, and Computer Architecture. As part of his current research work, he is engaged in the design and development of a “64-bit RISC-V ASIC”.

Email: dsudipta@iisc.ac.in

Kuruvella Abhishek Seshan is currently pursuing his M.Tech in Microelectronics and VLSI Design (2024-2026). He earned his B.Tech in Electronics and Communication Engineering from Gayatri Vidya Parishad College of Engineering, Visakhapatnam, Andhra Pradesh, in 2023. His academic and research interests lie in Digital VLSI Design, Digital System Design, and Computer Architecture. As part of his academic project work, he is working on “Floorplanning Strategies for FPGA Designs”, aiming to optimize performance and resource utilization in programmable logic devices.

Email: abhisheksk@iisc.ac.in

Akash is currently pursuing his M.Tech in Microelectronics and VLSI Design (2024–2026). He completed his B.Tech in Electrical Engineering from VSSUT, Odisha in 2021. His areas of interest include Digital VLSI Design, Digital System Design,  Computer Architecture and Hardware for Neural Network for Image Processing application. He is presently working on the design and development of a “Hardware Accelarator for Image De-Noising” as part of his academic and research pursuits.

Email: akashsahu@iisc.ac.in

Aniket Sarkar is currently pursuing his M.Tech in Microelectronics and VLSI (2024–2026). He holds a B.Tech in Electronics and Communication Engineering from Vellore Institute of Technology (VIT), Vellore. His areas of interest include Digital System Design, Digital VLSI, Robotics, and Multirotors. He is presently working on the development of a hardware accelerator for regular expression pattern matching using High-Level Synthesis (HLS).

Email: aniketsarkar@iisc.ac.in