Synchronization Support in 64-bit Out-Of-Order Superscalar Dual-Core RISC-V Processor
S. Yadav, M. Kumar, S. S, S. S. Garag and K. Varghese, “Synchronization Support in 64-bit Out-Of-Order Superscalar Dual-Core RISC-V Processor”, 2024 IEEE 9th International Conference for Convergence in Technology (I2CT), Pune, India, 2024, pp. 1-7, doi: 10.1109/I2CT61223.2024.10543746., https://ieeexplore.ieee.org/document/10543746
High Throughput Hardware Acceleration for Image Generation using HLS,
Bhanu Prasad A and Kuruvilla Varghese, “High Throughput Hardware Acceleration for Image Generation using HLS”, 2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Hyderabad, India, 2023, pp. 309-313, doi: 10.1109APCCAS60141.2023.00076., https://ieeexplore.ieee.org/document/10509914
Efficient Hardware Design of Parameterized Posit Multiplier and Posit Adder
Sadhu Sai Ram and Kuruvilla Varghese, “Efficient Hardware Design of Parameterized Posit Multiplier and Posit Adder”, 2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Hyderabad, India, 2023, pp. 343-347, doi: 10.1109APCCAS60141.2023.00083., https://ieeexplore.ieee.org/document/10509943
An FPGA Based Accelerator of the Bi-Directional Wavefront Algorithm for Pairwise Sequence Alignment
Ajay S, Praveen V S and K. Varghese, “An FPGA Based Accelerator of the Bi-Directional Wavefront Algorithm for Pairwise Sequence Alignment”, 2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Hyderabad, India, 2023, pp. 40-44, doi: 10.1109APCCAS60141.2023.00021., https://ieeexplore.ieee.org/document/10509910
Resource-Efficient TCAM Implementation Using SRAM
Ennampelli, M., Varghese, K. (2024),“Resource-Efficient TCAM Implementation Using SRAM”,In: Lenka, T.R., Saha, S.K., Fu, L. (eds) Micro and Nanoelectronics Devices, Circuits and Systems. MNDCS 2023. Lecture Notes in Electrical Engineering, vol 1067. Springer, Singapore. pp 201-210, (Honorable Mention Award), https://link.springer.com/chapter/10.1007/978-981-99-4495-8_15
Design of a Multi-Core Compatible Linux Bootable 64-bit Out-of-Order RISC-V Processor Core
Sajin S, Shubham Sunil Garag, Anuj Phegade, Deepshikha Gusain, and Kuruvilla Varghese, “Design of a Multi-Core Compatible Linux Bootable 64-bit Out-of-Order RISC-V Processor Core”, 2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID), 2023, Hyderabad, India, 8-12 Jan 2023.pp. 42-47, DOI: 10.1109/VLSID57277.2023.00023, https://ieeexplore.ieee.org/document/10089948
High-Level Synthesis of Geant4 Particle Transport Application for FPGA
Ramakant Joshi, Kuruvilla Varghese, “High-Level Synthesis of Geant4 Particle Transport Application for FPGA”25th Euromicro Conference on Digital System Design (DSD), 2022, pp. 75-83, DOI: 10.1109/DSD57027.2022.00020., https://ieeexplore.ieee.org/document/9996703
A Soft RISC-V Vector Processor for Edge-AI
Naveen Chander, Kuruvilla Varghese, “A Soft RISC-V Vector Processor for Edge-AI”, 2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID), 2022, pp. 263-268, DOI:10.1109/VLSID2022.2022.00058., https://ieeexplore.ieee.org/document/9885953
Hardware Accelerator for Capsule Network based Reinforcement Learning
Dola Ram, Suraj Panwar, Kuruvilla Varghese, “Hardware Accelerator for Capsule Network based Reinforcement Learning”, 2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID), 2022, pp. 162-167, DOI: 10.1109/VLSID2022.2022.00041. (Nripendra Nath Biswas Best Student Paper Award), https://ieeexplore.ieee.org/document/9885863
High Throughput Hardware for Hoeffding Tree Algorithm with Adaptive Naive Bayes Predictor
A. Antony, Devi. A, and K. Varghese, “High Throughput Hardware for Hoeffding Tree Algorithm with Adaptive Naive Bayes Predictor”, 2021 6th International Conference for Convergence in Technology (I2CT), 2021, pp. 1-6, DOI: 10.1109/I2CT51068.2021.9418100., https://ieeexplore.ieee.org/document/9418100
Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA
Gokulan T, Akshay Muraleedharan, and Kuruvilla Varghese, “Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA”, Euromicro Conference on Digital System Design (DSD) 2020, Virtual Event, 26-28 August 2020, pp. 340-343, DOI: 10.1109/DSD51259.2020.00062, https://ieeexplore.ieee.org/document/9217851
A RISC-V ISA Compatible Processor IP
A. Birari, P. Birla, K. Varghese, and A. Bharadwaj, “A RISC-V ISA Compatible Processor IP”, 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, 2020, pp. 1-6, DOI: 10.1109/VDAT50263.2020.9190558., https://ieeexplore.ieee.org/document/9190558
Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network
Nimish Shah, Paragkumar Chaudhari, and Kuruvilla Varghese, “Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network”, IEEE Transactions on Neural Networks and Learning Systems, Volume 29, Issue 12, pp. 5922-5934, December 2018, DOI: 10.1109/TNNLS.2018.2815085., https://ieeexplore.ieee.org/document/8333773/
FPGA Based Reconfigurable Coprocessor for Deep Convolutional Neural Network Training
Sajna Remi Clere, Sachin Sethumadhavan, Kuruvilla Varghese, “FPGA Based Reconfigurable Coprocessor for Deep Convolutional Neural Network Training”, 2018 21st Euromicro Conference on Digital System Design (DSD), Prague, Czech Republic, August 2018, pp. 381-388, DOI: 10.1109/DSD.2018.00072, https://ieeexplore.ieee.org/document/8491843/
A RISC-V ISA Compatible Processor IP for SoC
Suseela Budi, Pradeep Gupta, Kuruvilla Varghese, Amrutur Bharadwaj, “A RISC-V ISA Compatible Processor IP for SoC”, 2018 International Symposium on Devices, Circuits and Systems (ISDCS), Indian Institute of Engineering Science and Technology, Shibpur, March 29-31 2018, pp. 1-5, Kolkata, India. DOI: 10.1109/ISDCS.2018.8379629., https://ieeexplore.ieee.org/document/8379629/
A High-throughput Clock-less Architecture for Soft-Output Viterbi Detection
A. Dey, S. Jose, K. Varghese, and S. G. Srinivasa, “A High-throughput Clock-less Architecture for Soft-Output Viterbi Detection”, 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, USA, Aug. 2017, pp. 779-782, DOI: 10.1109/MWSCAS.2017.8053039., https://ieeexplore.ieee.org/document/8053039/
A Custom Designed RISC-V ISA Compatible Processor for SoC
Kavya Sharat, Sumeet Bandishte, Kuruvilla Varghese, Amrutur Bharadwaj, “A Custom Designed RISC-V ISA Compatible Processor for SoC”, Custom Designed RISC-V ISA Compatible Processor for SoC”, 21st International Symposium on VLSI Design and Test (VDAT-2017), 29 June – 2 July 2017, IIT Roorkee, India, 29 June – 2 July 2017, Communications in Computer and Information Science, vol 711. Springer, Singapore, pp. 570-577, DOI: 10.1007/978-981-10-7470-7_55, https://link.springer.com/chapter/10.1007/978-981-10-7470-7_55
RISC-V Compatible Processor Ip for SoC
Pradeep Gupta, Suseela Budi, Kuruvilla Varghese, and Amrutur Bhardwaj, “RISC-V Compatible Processor Ip for SoC”, A RISC-V Compatible Processor Ip for SoC”, RISC-V International Conference, April 2017, IIT Madras, Chennai., http://rise.cse.iitm.ac.in/ric2017/index.html
Flow Control for Onboard Solid State Recorder
Siddhartha B. Rai, Srinidhi M.S., Kuruvilla Varghese, and Srividhya R, “Flow Control for Onboard Solid State Recorder”, 4th International Conference on Electronics and Communication Systems, 24-25 Feb 2017, Coimbatore, India, pp. 65-69., http://ieeexplore.ieee.org/document/8067838/
Accelerating method of moments based package-board 3D parasitic extraction using FPGA
Anant Devi, Maulik Gandhi, Kuruvilla Varghese, and Dipanjan Gope, “Accelerating method of moments based package-board 3D parasitic extraction using FPGA”, Microwave and Optical Technology Letters, Volume 58, Issue 4, pp. 776-783, April 2016., http://onlinelibrary.wiley.com/doi/10.1002/mop.29660/abstract
Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA
Sriram Venkateshan, Alap Patel, and Kuruvilla Varghese, “Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 10, pp. 2221-2232, Oct. 2015, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6933936
Hardware Accelerator for 3D Method of Moments based Parasitic Extraction
Anant Devi, Maulik Gandhi, Kuruvilla Varghese, and Dipanjan Gope, “Hardware Accelerator for 3D Method of Moments based Parasitic Extraction”, The 2013 IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) symposium, December 2013, Nara, Japan. pp. 100-103., http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6724399
Transparent FPGA based Device for SQL DDoS Mitigation
Karthikeyan P, Srijith Haridas, and Kuruvilla Varghese, “Transparent FPGA based Device for SQL DDoS Mitigation”, International Conference on Field-Programmable Technology 2013 (ICFTP 2013), December 2013, Kyoto, Japan. pp. 82-89., http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6718334
HD Resolution Intra Prediction Architecture for H.264 Decoder
Jimit Shah, K.S. Raghunandan, and Kuruvilla Varghese, “HD Resolution Intra Prediction Architecture for H.264 Decoder”, 25th IEEE International Conference on VLSI Design VLSID 2012, January 2012, Hyderabad, India. pp.107 – 112., http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6167737
A Scalable Network Port Scan Detection System on FPGA
Tejasvi Anand, Yagnesh Waghela, and Kuruvilla Varghese, “A Scalable Network Port Scan Detection System on FPGA”, IEEE International Conference on Field-Programmable Technology (FPT’11). December 2011, New Delhi, India. pp. 1-6., http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6132712
Space Efficient Diagonal Linear Space Sequence Alignment
Gandhi Arpit, Raghavendra Adiga and Kuruvilla Varghese, “Space Efficient Diagonal Linear Space Sequence Alignment”, 10th IEEE International Conference on Bioinformatics and Bioengineering (BIBE 2010) 3 June 2010, Philadelphia, pp. 244-249., http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5521681
In-Channel Flow Control Scheme for Network-on-Chip
Vrishali Vijay Nimbalkar, and Kuruvilla Varghese, “In-Channel Flow Control Scheme for Network-on-Chip”, 16th Euromicro Conference on Digital Systems Design (DSD 2010), September 2010, France, pp. 459-466., http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5615566
Area Optimized H.264 Intra Prediction Architecture for 1080p HD Resolution
Jimit Shah, Komanduri S. Raghunandan and Kuruvilla Varghese, “Area Optimized H.264 Intra Prediction Architecture for 1080p HD Resolution”, 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2010), July 2010, France, pp: 120-125., http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5540989&tag=1
Power Optimal Network-on-Chip Interconnect Design
Vikas. G, Joy Kuri, and Kuruvilla Varghese, “Power Optimal Network-on-Chip Interconnect Design”, 22nd IEEE International SOC Conference, September 2009, Northern Ireland, UK, pp. 147-150., http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5398071
Dynamically Reconfigurable Regular Expression Matching Architecture
Divyasree J, Rajashekar H, and Kuruvilla Varghese, “Dynamically Reconfigurable Regular Expression Matching Architecture”, 20th IEEE International Conference on Application-specific Systems, Architectures and Processors 2008 (ASAP 2008), July 2008, Leuven, Belgium, pp. 120-125., http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4580165
A Scalable High Throughput Firewall in FPGA
Gajanan Jedhe, Arun Ramamoorthy and Kuruvilla Varghese, “A Scalable High Throughput Firewall in FPGA”, The 16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2008 (FCCM’08), April 2008, California, USA, pp. 43-52., http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4724888