Kuruvilla Varghese is a Chief Research Scientist at the Department of Electronic Systems Engineering (DESE, formerly CEDT), Indian Institute of Science, Bangalore. He is working at DESE since 1989. His main research interests are in Digital VLSI Systems and Computer Networks. Presently he is working on High performance accelerators for Machine Learning, Bioinformatics, and Networking using Field Programmable Gate Arrays (FPGA) in Reconfigurable Computing Lab at DESE.

Expertise

Digital Systems, VLSI, High Performance Accelerators, Computer Networks

Address and contact details

Department of Electronic Systems Engineering (DESE),
Indian Institute of Science (IISc), Bangalore 560 012. India.
Tel: + 91 80 2293 3092.

Email: kuru@iisc.ac.in.

Akhila is pursuing M Tech (Res) in Electronic Systems Engineering (2024-2027). She received her Bachelor of Engineering in Electronics and Communication Engineering from National Institute of Technology Andhra Pradesh, Tadepalligudem in 2024. She is currently working on “Hardware Accelerator for BiWFA using HLS”.

Email: akhilac@iisc.ac.in

Shivangi is pursuing M.Tech in Electronic Product Design (EPD) (2025–2027). She received her Bachelor of Technology in Electrical Engineering from the Indian Institute of Technology (IIT) Kharagpur, West Bengal. Her academic interests include VLSI, FPGA design, Machine Learning, and Power Electronics. She is currently working on “FPGA-based Controller for Self-Driven Vehicle”, focusing on enabling low-latency, energy-efficient autonomous vehicle control using FPGA technology.

Email: shivangia@iisc.ac.in

Shreevathsa is pursuing M.Tech in Electronic Product Design (EPD) (2025–2027). He received his Bachelor of Technology in Electrical and Electronics Engineering from the National Institute of Technology Karnataka (NITK), Surathkal. His research interests include Digital System Design, Machine Learning, Computer Vision, and Computer Architecture. He is currently working on “FPGA-based Controller for Self-Driven Vehicle”, focusing on enabling low-latency, energy-efficient autonomous vehicle control using FPGA technology.

Email: shreevathsak@iisc.ac.in

Dev is pursuing M.Tech in Electronic Systems Engineering (ESE) (2025–2027). He received his Bachelor of Technology in Electrical Engineering from the National Institute of Technology (NIT) Surat. His research interests include Computer Architecture, Electronic Systems, and Digital System Design. He is currently working on “32-Bit RISC-V ASIC”, aiming to design and tape out a high-performance 32-bit RISC-V ASIC for embedded applications.

Email: devpatel@iisc.ac.in

Nilanjan is pursuing M.Tech in Electronic Systems Engineering (ESE) (2025–2027). He received his Bachelor of Engineering in Electronics and Telecommunication Engineering from Jadavpur University, West Bengal. His academic interests include Computer Architecture, Digital System Design, Embedded Systems, and Electronic Systems. He is currently working on “AXI Interconnect IP for ASIC”, focusing on the design and implementation of a high-performance AXI interconnect for heterogeneous System-on-Chip (SoC) architectures.

Email: nilanjandas@iisc.ac.in

Paras is pursuing M.Tech in Electronic Systems Engineering (ESE) (2025–2027). He received his Bachelor of Technology in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi. His academic interests include Electronic Systems, Digital System Design, and Computer Architecture. He is currently working on “32-Bit RISC-V ASIC”, aiming to design and tape out a high-performance 32-bit RISC-V ASIC for embedded applications.

Email: paraschopra@iisc.ac.in

Pothina Gayathri is pursuing M.Tech in Microelectronics and VLSI Design (MVLSI) (2025–2027). She received her Bachelor of Technology in Electronics and Communication Engineering from Raghu Engineering College, Visakhapatnam. Her research interests include Computer Architecture, Digital VLSI and RTL Design. She is currently working on “Vector Extension Implementation for RISC-V”, focusing on developing a custom out-of-order vector coprocessor to maximize throughput for vector instructions through data-level parallelism.

Email: gayathri1@iisc.ac.in

Ankush is pursuing M.Tech in Microelectronics and VLSI Design (MVLSI) (2025–2027). He received his Bachelor of Technology in Electrical Engineering from the Indian Institute of Technology (IIT) Bhubaneswar. His research interests include Digital System Design and Computer Architecture. He is currently working on “64-bit RISC-V ASIC”, with the goal of designing and taping out an ASIC implementation of a 64-bit out-of-order superscalar RISC-V processor.

Email: ankushjohn@iisc.ac.in

Ayush is pursuing M.Tech in Microelectronics and VLSI Design (MVLSI) (2025–2027). He received his Bachelor of Technology in Electrical Engineering from the Indian Institute of Technology (IIT) Kanpur. His academic interests include Computer Architecture and Digital System Design. He is currently working on “Vector Extension Implementation for RISC-V”, aiming to develop a custom out-of-order vector coprocessor that exploits data-level parallelism to maximize vector instruction throughput.

Email: ayush1@iisc.ac.in