64-bit 4-wide Out-of-Order Processor core

  • RV64IMAFDCSU Instruction set
  • Support 9 Stage pipeline (Fetch, Pre-decode, Checking, Decode, Rename, Dispatch, Issue, Execute and Retire)
  • Decode and Issue up to 4 instructions per cycle Out-of-Order execution and In-Order commit using ROB
  • Six execution units with split functionality
  • Branch prediction using BTB and 2-bit direction predictor
  • Register renaming to avoid dependency
  • 16 KiB 4-Way set-associative VIPT I-Cache & PIPT D-Cache
Resource Utilization Available Utilization %
LUT 250375 303600 82.47
LUTRAM 6507 130800 4.97
FF 89536 607200 14.75
DSP 20 2800 0.71
IO 200 700 28.57
PLL 1 14 7.14

A 32 bit, 5-stage Pipeline Scalar RISC-V

    • Supports RV32G (RV32IMAFD) instructions
    • Integrated Floating-Point Unit
    • Split I and D (Instruction and Data) caches
    • Virtual Memory, Data and Instruction TLBs (DTLB & ITLB)
    • Branch Prediction Unit
    • System Counters
    • Interrupt controller with four levels of pre-emptive priority
    • Main Memory with Error Control Coding
    • Wishbone B.3 Bus Protocol

A Softcore RISC-V Vector Processor for Edge AI

Performance on Neural Networks Speedup Energy Improvement
Multi-layer Perceptron 40.7x ~33x
Convolutional Neural Network 19.53x ~16x

 

On-chip Power Static Dynamic Total
Vector CPU 264 mW 333 mW 597 mW
Scalar CPU 263 mW 233 mW 496 mW

Runtime Programmable Coprocessor for DCNN

  • Runtime Programmable
  • Computational throughput of more than 140 G operations/s
  • Max image size: 256 × 256, filter size: 16 × 16, Convolution stride: 1
  • Maximum of 32 layers in network and 256 filters in a layer.
  • Rectified linear unit (ReLU) as nonlinearity and max-pooling of size 2 × 2 and stride 2
Input feature size Kernel size Throughput (Gop/s)
ACM’15
(Virtex-7)		 ITNNLS’16
(Kintex-7)		 Our work
(Virtex-7)
224 x 224 11 x 11 27.5 122 149.4
55 x 55 5 x 5 83.8 105 151
27 x 27 3 x 3 78.8 69 183.5
12 x 12 3 x 3 77.9 32 140.5
7 x 7 3 x 3 – 5.9 105.2

32-bit RISC-V ASIC Architecture

  • Pipeline Components
  • ICACHE/DCACHE Support
  • CSR support with RISCV Privileged Spec compliance
  • CLINT based interrupt controller
  • Hardware interrupt handling
  • MMU Support, MPU Support
  • Debug Support
  • User defined memory map
All Projects

Address:

Room No.: 221
First Floor
Department of Electronic Systems Engineering
Division of EECS
Indian Institute of Science
Bangalore 560012, INDIA

 

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