Born and brought up in Jodhpur, Rajasthan, Vipin is a project scientist in Prof. Mayank Shrivastava’s research group at IISc Bangalore. Before joining as a project scientist in IISc, Vipin was a PhD student at IIT Jodhpur where he worked with Prof. Shree Prakash Tiwari and was also associated with IISc Bangalore as an intern. Vipin obtained his bachelor’s degree in electronics and communication engineering from Rajasthan University, Jaipur and master’s degree in VLSI Design from Malviya National Institute of Technology, Jaipur. Vipin holds a teaching experience of 2 years at JIET Group of Institutions as an assistant professor. In his spare time Vipin loves to meditate, playing tennis and badminton and enjoys spending time with his family the most.


  1. Sayak Dutta Gupta, V Joshi, S Raghavan, M. Shrivastava, ‘UV-Assisted Probing of Deep-Level Interface Traps in GaN MISHEMTS and Their Role in Threshold Voltage & Gate Leakage Instabilities’, accepted in 2019 IEEE International Reliability Physics Symposium (IRPS), 2019
  2. V. Joshi, S. P. Tiwari and M. Shrivastava, “Part I: Physical Insight Into Carbon-Doping-Induced Delayed Avalanche Action in GaN Buffer in AlGaN/GaN HEMTs,” in IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 561-569, Jan. 2019. doi: 10.1109/TED.2018.2878770 URL:
  3. V. Joshi, S. P. Tiwari and M. Shrivastava, “Part II: Proposals to Independently Engineer Donor and Acceptor Trap Concentrations in GaN Buffer for Ultrahigh Breakdown AlGaN/GaN HEMTs,” in IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 570-577, Jan. 2019. doi: 10.1109/TED.2018.2878787 URL:
  4. V. Joshi, B. Shankar, S. P. Tiwari and M. Shrivastava, “Dependence of avalanche breakdown on surface & buffer traps in AlGaN/GaN HEMTs,” 2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kamakura, 2017, pp. 109-112.doi: 10.23919/SISPAD.2017.8085276. URL:
  5. V. Joshi, A. Soni, S. P. Tiwari and M. Shrivastava, “A Comprehensive Computational Modeling Approach for AlGaN/GaN HEMTs,” in IEEE Transactions on Nanotechnology, vol. 15, no. 6, pp. 947-955, Nov. 2016. doi: 10.1109/TNANO.2016.2615645 URL:
  6. A. Tyagi, V. Joshi and S. P. Tiwari, “A wedge tunnel FET device for larger tunneling area and improved ON current,” 2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO), Rome, 2015, pp. 913-915. doi: 10.1109/NANO.2015.7388763 URL:
  7. A.K. Mahato, D. Bharti, V. Joshi, V. Raghuwanshi and S. P. Tiwari, “Comprehensive analysis of TIPS-Pentacene: Polymer blend organic field-effect transistor for device and circuit simulation,” 2017 IEEE 12th Nanotechnology Materials and Devices Conference (NMDC), Singapore, 2017, pp. 194-195. doi: 10.1109/NMDC.2017.8350553 URL:

Awards and Achievements:

  1. Scored 507 in GATE 2009 with 96.56 percentile and AIR 1458
  2. Awarded double star performance in Academic & Skill Development program for achieving more than 90% university result for the session 2011-12