A. New Discovery yields a giant leap in graphene transistor performance: My group has made a big jump in understanding the quantum nature of graphene’s interface with outside world. The team has studied how the overlap of atomic orbitals between Carbon and metal atoms affects the graphene-metal interface. The study has enabled to invent novel techniques to engineer graphene contact that has the lowest recorded contact resistance. As a result of this discovery and subsequent inventions, while breaking several records – including the one from IBM’s research centre in T. J. Watson, USA – it has eventually allowed achieving the highest graphene transistor performance.
B. Deeper insights into Electron-Phonon Transport Probed at nano-second time scale: We have developed a new technique to probe electron – phonon interaction at nano-second time scales. The idea is to isolate carrier transport from external or induced perturbations, which develop as a function of time, example phonon bath, and systematically study dynamics of electron transport. This is the first time any research group has developed and reported such a technique. Using this method we have reported, for the first time, (i) remote joule heating of cold contact and its impact on carrier transport through 1D and 2D materials, (ii) time constant of contact and channel annealing, (iii) dynamics of thermal failure and (iv) changeover from ballistic to diffusive transport attributed to scattering induced phonon bath at the nanosecond time scale.
C. Breakthrough in Nanometer scale transistor technology: My group has demonstrated a new transistor design which can significantly improve the chip performance and it’s scalability beyond 10nm technology node. It works at lower voltages, draws 15 times less charge in idle state and offers higher frequency performance. These factors ensure longer battery life, smaller chip area (lighter), lower cost and higher speed. This new device is expected to reduce chip cost by four to five times for IoT applications when compared to current day technology. In simple terms it offers a newer technology which is cheaper and can be manufactured without putting capital, that is newer manufacturing plants, and at the same time it offers significantly better performance and scalability.
D. New Class of Integrated Power Transistors: For the first time, a novel Drain extended tunnel FET device (DeTFET) is disclosed, while addressing need for high voltage / high power devices for System on Chip and automotive applications in beyond FinFET technology nodes. Operation of the proposed DeTFET device is presented with physics of band-to-band tunnelling and associated carrier injection. Device’s intrinsic (DC/switching), analog and RF performance compared with state of the art drain extended NMOS device (DeNMOS) shows that the proposed device offers 15× better subthreshold slope, 8× lower OFF state leakage, 2× higher ON current, absence of channel length modulation and drain induced barrier lowering, while keeping 2.5× lower threshold voltage. This results into significantly better ON resistance for a range of gate voltages, higher transconductance, orders of magnitude higher intrinsic transistor gain and better RF characteristics, when compared to the DeNMOS device. The patented (and later published) device is expected to improve the performance of future power ASICs.
E. ESD reliability of newer material based transistor technologies: ESD is considered to be one of the most fundamental reliability issue associated with semiconductors. We have explored ESD reliability of graphene, CNT, Pentacene and a-Si:H like new material based devices and GaN based high electron mobility transistors. My group has published majority of papers in this field.
F. Performance and reliability advancement of LDMOS devices: It’s been over 40 years when the first power MOSFET was invented. However, till the recent years, performance and reliability of these devices was considered to independent phenomena and was always studied / addressed independently. In our recent works, for the first time, we have attempted to find common design knobs to tackle both the challenges. In this direction, we have (i) unified physics of quasi-saturation in power MOSFETs, which was considered to be a fundamental bottleneck; (ii) using the unified physics we have shows different ways by which quasi-saturation can be mitigated, which improves device performance and (iii) have come-up with few design proposals, which improves the device performance as well as reliability. These recent works are expected to change the way power MOSFETs were designed and used in integrated circuits.
G. Record High Performance 600V e-mode GaN HEMT Technology (paper under review): For the first time, a high- κ ternary gate oxide has been demonstrated as a potential candidate for achieving e-mode operation in AlGaN/GaN HEMTs. The ternary oxide was found to be similar to p-GaN gate for achieving e-mode HEMT operation. However it allowed better channel control as a thin ternary oxide in conjunction with partial recess was capable to achieve a threshold voltage of 0.5V. Using the developed gate oxide, record high performance 600V class of e-mode device has been demonstrated with ON current ~400mA/mm, subthreshold slope of 73mV/dec, Ron = 8.9Ωmm, interface trap density < 1010 mm-2eV-1 and gate leakage below 200nA/mm at the OFF state breakdown. Based on experimental finding, a hybrid gate stack which combines pGaN technology with the developed dielectric for e-mode operation, has been proposed.
H. Deeper Insights in GaN HEMT Reliability Issues: Through 4 IRPS papers and 1 paper in IEDM (2018) we have revealed deeper insights and have highlighted fundamental issues related to safe operating area reliability of GaN HEMTs. Besides, we have also developed deeper insights into the physics and role of C-doping of GaN buffers in AlGaN/GaN HEMTs. These insights have allowed us to engineer C-doping profile across GaN Epi-stack with improves the breakdown voltage as well as mitigates current collapse phenomena at the same time, without compromising on leakage current (paper to appear in TED).
I. High Performance 2D Material FET Technology (paper under review): For the first time, atomic orbital overlap engineering for TMDs is proposed, which significantly improves the overall transistor performance without any hidden compromise. Understanding low temperature decomposition of H2S on TMD surface and quantum chemistry between transition metals, chalcogenides & contact metals have enabled the proposed atomic orbital overlap engineering to improve channel as well as contact performance and passivate/cure dangling bonds present in defected regions. These collectively have improved MoS2, WS2, MoSe2 and WSe2 FET’s characteristics by significant margins. Record high ON current for WS2 FET (240 mA/mm), at room temperature is demonstrated. Moreover, an overall record high performance improvement is achieved for MoS2, WS2, MoSe2 and WSe2 transistors. The proposed approach has been validated statistically across large set of devices. Besides, a novel way to get p-channel operation in WSe2 devices have been demonstrated.