Dr. Nikhil K S

nikhilks@iisc.ac.in

Nikhil grew up in Thiruvananthapuram, Kerala and pursued B.Tech in Electronics and Communication  Engg. from University  of Kerala. He has done Master’s in VLSI DESIGN from College of Engineering Guindy, Chennai. He has obtained PhD in Electrical Engineering from IIT Madras, Chennai in 2018 . Thesis entitled “ Modeling and design of breakdown voltage of SOI-LDMOS transistors for power amplifier applications”.

Nikhil joined Mayank Shrivastava Device Laboratory (MSDLab) as a Research Associate (RA) in one of the project in September 2018. His current research interests include the simulation and compact modeling of LDMOS and Drain extended FinFETs. He is also interested in the modeling of electrostatic discharge in power devices.

Journals

1) K. S. Nikhil, N. DasGupta, A. DasGupta, and, A. Chakravorty. “SOI-LDMOS Transistors With Optimized Partial n + Buried Layer for Improved Performance in Power Amplifier Applications,” Electron Devices, IEEE Transactions on, vol. 65, no. 11, pp. 4931-4937, Nov 2018.

2) K. S. Nikhil, N. DasGupta, A. DasGupta, and, A. Chakravorty. “Analysis and Modeling of the Snapback Voltage for Varying Buried Oxide Thickness in SOI-LDMOS Transistors,” Electron Devices, IEEE Transactions on, vol. 63, no. 10, pp. 4003-4010, Oct 2016.

3) N. Prasad, P. Sarangapani, K. S. Nikhil, N. DasGupta, A. DasGupta, and, A. Chakravorty. “An Improved Quasi-Saturation and Charge Model for SOI-LDMOS Transistors,” Electron Devices, IEEE Transactions on, vol. 62, no. 3, pp. 919-926, March 2015.

4) K. S. Nikhil and, B. Bindu. “Feasibility of Study of Conical Channel Nanowire MOSFETs for Improved Performance,” Procedia Engineering, vol. 38, pp. 2364-2370, 2012.

Conferences

1) S. Gupta, K. S. Nikhil, A. Chakravorty, A. DasGupta, and, N. DasGupta. “Prediction of IMD behavior in LDMOS transistor amplifiers using a physics-based large signal compact model,” IEEE 3rd International Conference on Emerging Electronics, Mumbai, Dec 2016.

2) K. S. Nikhil and, B. Bindu. “Performance Optimization of GAA Silicon Nanowire MOSFETs with Dual Gate,” IEEE 3rd International Conference on Electronics Computer Technology, Nagercoil, 2012.