Milova Paul

milova@iisc.ac.in

Milova grew up in New Delhi, and pursued B.Tech in Electronics and Communication from MD University, Rohtak. Following this, she obtained her M.Tech in VLSI & Embedded Systems from Delhi Technological University in 2014. She then moved to Bangalore to undertake a PhD under the supervision of Prof. Mayank Shrivastava, focusing on the Electrostatic Discharge and Latch-Up Reliability of non-planar CMOS technology nodes, ranging from devices like FinFET, III-V or SiGe based quantum well channel FinFET and Gate-All-Around (GAA) or nanowire devices. In her spare time, she enjoys reading, listening to music, and exploring different cuisines.

Publications:

  • M. Paul, C. Russ, B. S. Kumar, H. Gossner and M. Shrivastava, “Physics of Current Filamentation in ggN- MOS Devices Under ESD Condition Revisited”. IEEE Transactions on Electron Devices, vol. 65, no. 7, pp. 2981-2989, July 2018.
  • M. Paul, B. S. Kumar, C. Russ, H. Gossner and M. Shrivastava, “Challenges & Physical Insights into the Design of Fin Based SCRs and a Novel Fin-SCR for Efficient On-Chip ESD Protection”. IEEE Transactions on Electron Devices, 2018.
  • M. Paul, C. Russ, B. S. Kumar, H. Gossner and M. Shrivastava, “Physics of Current Filamentation in ggN- MOS Revisited: Was Our Understanding Scientifically Complete?” 30th International Conference on VLSI De- sign and 16th International Conference on Embedded Systems (VLSID), Hyderabad, 2017, pp. 391-394.
  • M. Paul, B. S. Kumar, C. Russ, H. Gossner and M. Shrivastava, “FinFET SCR: Design challenges and novel fin SCR approaches for on-chip ESD protection”. 39th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Tucson, AZ, 2017, pp. 1-6.
  • M. Paul, B. S. Kumar, H. Gossner and M. Shrivastava, “Contact and junction engineering in bulk FinFET technology for improved ESD/latch-up performance with design trade-offs and its implications on hot carrier reliability”. IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA, 2018, pp. 3E.3- 1-3E.3-6.
  • B. S. Kumar, M. Paul, H. Gossner and M. Shrivastava, “Performance and reliability insights of drain ex- tended FinFET devices for high voltage SoC applications”. IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Chicago, IL, 2018, pp. 72-75.
  • B. S. Kumar, M. Paul, and M. Shrivastava, “On the design challenges of drain extended FinFETs for advance SoC integration”. 22nd International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kamakura, Japan, 2017, pp. 189-192.
  • B. S. Kumar, M. Paul, H. Gossner and M. Shrivastava, “Physical Insights into the ESD behavior of Drain Extended FinFETs”. 40th EOS/ESD Symposium 2018, Reno, Nevada, USA.
  • M. Paul, B. S. Kumar, K. K. Nagothu, P. Singhal, H. Gossner and M. Shrivastava, “Fin Enabled Drain Ex- tended FinFET SCR for self-protected designs”. (under submission) in IEEE Transactions on Electron Devices.
  • M. Paul, B. S. Kumar, H. Gossner and M. Shrivastava, “Hybrid Contact & Junction Engineering in Bulk FinFET Technology for improved ESD/Latch-Up Performance and HCI Reliability”. (under submission) in IEEE Transactions on Electron Devices.
  • M. Paul, B. S. Kumar, H. Gossner and M. Shrivastava, “ESD and HCI Behavior of Stacked Bulk FinFETs”.

 

(under submission) in IEEE Transactions on Electron Devices.

  • M. Paul, C. Russ, H. Gossner and M. Shrivastava, “Insights into the turn-on behavior of mutli-fin arrange- ment in FinFET Technology under ESD conditions”. (under submission) in IEEE Transactions on Electron De- vices.
  • B. S. Kumar, M. Paul, H. Gossner and M. Shrivastava. “Physical Insights, challenges & device design of high voltage drain extended FinFET transistors”. (under submission) in IEEE Transactions on Electron Devices.
  • B. S. Kumar, M. Paul, H. Gossner and M. Shrivastava. “Electrostatic Discharge & Hot carrier reliability of High Voltage Drain extended FinFET transistors”. (under submission) in IEEE Transactions on Electron Devices.

Patents

  • M. Paul, M. Shrivastava, B. S. Kumar, C. Russ and H. Gossner, “Dual Fin Silicon Controlled Rectifier (SCR) Electrostatic Discharge (ESD) Protection Device”. US Patent Pending, Application No: 15/883,306, Filed on: 30-Jan-18 (Indian Patent, Application No 201741003771, Filed on 1st Feb. 2017).
  • M. Shrivastava, M. Paul, C. Russ and H. Gossner, “Non-planar Electrostatic Discharge (ESD) Protection Devices With Nano Heat Sinks”. US Patent Application No: US20180226317A1, (Indian Patent, Application No 201741003773, Filed on 1st Feb. 2017).
  • M. Shrivastava, M. Paul, C. Russ and H. Gossner, “Low Trigger And Holding Voltage Silicon Controlled Rec- tifier (SCR) For Non-Planar Technologies”. US Patent Application No: US20180219007A1, (Indian Patent, Application No 201741003772, Filed on 1st Feb. 2017).
  • M. Shrivastava, M. Paul and H. Gossner, “FinFET SCR With SCR Implant Under Anode And Cathode Junctions”. US Patent Application No: US20180248025A1, (Indian Patent, Application No 201741006746, Filed on 25th Feb. 2017).
  • M. Shrivastava, M. Paul and H. Gossner, “Semiconductor devices and methods to enhance Electrostatic Dis- charge (ESD) robustness, latch-up, and hot carrier immunity”. US Patent Application No: US20180247929A1, (Indian Patent, Application No 201741006745, Filed on 25th Feb. 2017).

Awards:

  • Outstanding Paper Award, EOS/ESD Symposium, Sept
  • Honorable Mention Research Paper Award, VLSI Design Conference, Jan