Kranthi Nagothu
karmel@iisc.ac.in

Kranthi Nagothu is from the state of Andhra Pradesh, India. He obtained his B.Tech degree from Jawaharlal Nehru Technological University, Kakinada in 2012 and M.tech from National Institute of Technology Calicut, Kerala in 2014. He was with ST Micro Electronics, Noida as a graduate trainee from June, 2013 to July, 2014. Later he joined ANDCRG, DESE, IISc, as a research assistant. Currently he is pursuing his Ph.D from the same group. His research interests include exploration of Electro Static Discharge (ESD) behaviour of beyond CMOS technologies (Tunnel FETs and Graphene FETs) and power scalability issues in advanced High Voltage CMOS technologies specific to Silicon Controlled Rectifiers (SCR) in Laterally Double diffused MOS  (LDMOS) Devices. He likes to keep himself updated with the current affairs and enjoys playing cricket and cycling.

Publications:

Journals:

[1] N. K. Kranthi and M. Shrivastava, “ESD Behavior of Tunnel FET Devices,” in IEEE Transactions on Electron Devices, vol. 64, no. 1, pp. 28-36, Jan. 2017.

[2] K. K. Nagothu, A. Mishra, A. Meersha and M. Shrivastava, “On the ESD Behavior of Large-Area CVD Graphene Transistors: Physical Insights and Technology Implications,” in IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 743-751, Jan. 2019.

International Conferences:

[3] N. K. Kranthi, A. Mishra, A. Meersha and M. Shrivastava, “ESD behavior of large area CVD graphene RF transistors: Physical insights and technology implications,” 2017 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, 2017, pp. 3F-1.1-3F-1.6.

[4] N. K. Kranthi, A. Mishra, A. Meersha, H. B. Variar and M. Shrivastava, “Defect-Assisted Safe Operating Area Limits and High Current Failure in Graphene FETs,” 2018 IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA, 2018, pp. 3E.1-1-3E.1-5.

[5] N. K. Kranthi, A. Mishra, A. Meersha and M. Shrivastava, “On the ESD Reliability Issues in Carbon Electronics: Graphene and Carbon Nano Tubes,” 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), Pune, India, 2018, pp. 469-470.

[6] N. K. Kranthi, B. Sampath Kumar, Akram Salman, Gianlica Boselli and M. Shrivatava, “Physical Insights into the Low Current ESD Failure of LDMOS-SCR and Its Implication on Power Scalability” to be presented at 2019 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA.

[7] N. K. Kranthi, Akram Salman, Gianlica Boselli and M. Shrivatava, “Current Filament Dynamics Under ESD Stress in High Voltage (Bidirectional) SCRs and Its Implications on Power Law Behavior” to be presented at 2019 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA.

[8] R. Sinha, N. K. Kranthi, S. Sambandan and M. Shrivastava, “On the ESD behavior of pentacene channel organic thin film transistors,” 2017 39th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Tucson, AZ, 2017, pp. 1-6.

[9] A. Mishra, Adil meersha, N.K.Kranthi, K.Trivedi, Veena B, M. Shrivatava, “First Demonstration and Physical Insights into Time-dependent Breakdown of Graphene Channel and Interconnects” to be presented at 2019 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA.