Dr. Jhnanesh Somayaji B

jhnaneshs@iisc.ac.in

Dr. Jhnanesh Somayaji received his Ph.D from National Institute of Technology Karnataka (NITK Surathkal) in 2018. He was a visiting scholar at Indian Institute of Science Bangalore during 2015-2016. Currently, he works for Advanced Nano-devices & Computational Research Lab as a Project Associate at Department of Electronic systems Engineering, Indian Institute of Science, Bangalore. His research interests include Power semiconductors and circuits, submicron devices and technology.

Publications:

  1. Jhnanesh Somayaji B, Sampath Kumar B, M.S.Bhat and Mayank Shrivastava (2017). “Performance and reliability codesign for super-junction drain extended MOS devices”. IEEE Transaction on Electron Devices, 64(10), 4175-4183.
  2. Jhnanesh Somayaji B and M.S.Bhat (2017). “Triple RESURF DeMOS device design and its RF performance evaluation for sub-micron RF-SoC platform”. Journal of Low Power Electronics, American Scientific Publishers, 13(4), 669-677.
  3. Jhnanesh Somayaji B and M.S.Bhat (2016). “Analysis of implant parameters in high voltage triple RESURF DeMOS for advanced SoC applications”, Proceedings of IEEE Sixth International Symposium on Embedded Computing and System Design (ISED), 72 -76.
  4. Jhnanesh Somayaji and Kiran Bailey (2013). “Optimization of Gate Leakage for 22nm MOSFETs through Alternate High-k Materials using T-CAD simulations”, International Journal of VLSI and Embedded systems, 4(2), 293-298, ISSN: 2249 – 6556. Under Communication
  5. Jhnanesh Somayaji and M.S.Bhat. “Design considerations in double RESURF DeMOS for high performance RF – SoC Applications”, IETE Journal of Research.