B Sampath Kumar

boeila@iisc.ac.in

 

B Sampath kumar was born in Telangana, India and went to pursue his graduation from JNT University, Hyderabad. He later joined in VNIT, Nagpur to get mastered in Microelectronics and VLSI design. His research interest lies in designing of power devices in Non planar CMOS technology, co-designing through ESD and HCI reliability aspects. He also deals with device circuit co-design engineering. Prof. Mayank Shrivastava is the steward of his research work. He enjoys playing volley ball and cooking in free time.

Publications:

  • B. S. Kumar and M. Shrivastava, “Part I: On the unification of physics of quasi-saturation in LDMOS de- vices”. IEEE Transactions on Electron Devices, vol. 65, no. 1, pp. 191-198, January 2018.
  • B. S. Kumar and M. Shrivastava, “Part II: RF, ESD, HCI, SOA, and Self Heating Concerns in LDMOS Devices Versus Quasi-Saturation”. IEEE Transactions on Electron Devices, vol. 65, no. 1, pp. 199-206, January 2018.
  • J. Somayaji, B. S. Kumar, M. S. Bhat and M. Shrivastava, “Performance and Reliability Co-design for Super- junction Drain Extended MOS Devices”. IEEE Transactions on Electron Devices, vol. 64, no. 10, pp. 199-206, January 2018.
  • M. Paul, C. Russ, B. S. Kumar, H. Gossner and M. Shrivastava, “Physics of Current Filamentation in ggN- MOS Devices Under ESD Condition Revisited”. IEEE Transactions on Electron Devices, vol. 65, no. 7, pp. 2981-2989, July 2018.
  • B. S. Kumar, M. Paul, H. Gossner and M. Shrivastava, “Performance and reliability insights of drain ex- tended FinFET devices for high voltage SoC applications”. 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Chicago, IL, 2018, pp. 72-75.
  • B. S. Kumar, M. Paul, and M. Shrivastava, “On the design challenges of drain extended FinFETs for advance SoC integration”. 2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kamakura, Japan, 2017, pp. 189-192.
  • M. Paul, B. S. Kumar, C. Russ, H. Gossner and M. Shrivastava, “Challenges & Physical Insights into the Design of Fin Based SCRs and a Novel Fin-SCR for Efficient On-Chip ESD Protection”. to appear in IEEE Transactions on Electron Devices.
  • M. Paul, C. Russ, B. S. Kumar, H. Gossner and M. Shrivastava, “Physics of Current Filamentation in ggN- MOS Revisited: Was Our Understanding Scientifically Complete?” 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), Hyderabad, 2017, pp. 391-394.
  • M. Paul, B. S. Kumar, C. Russ, H. Gossner and M. Shrivastava, “FinFET SCR: Design challenges and novel fin SCR approaches for on-chip ESD protection”. 2017 39th Electrical Overstress/Electrostatic Discharge Sympo- sium (EOS/ESD), Tucson, AZ, 2017, pp. 1-6.
  • M. Paul, B. S. Kumar, H. Gossner and M. Shrivastava, “Contact and junction engineering in bulk FinFET technology for improved ESD/latch-up performance with design trade-offs and its implications on hot carrier reliability”. 2018 IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA, 2018, pp. 3E.3-1-3E.3-6.
  • B. S. Kumar, M. Paul, H. Gossner and M. Shrivastava, “Physical Insights into the ESD behavior of Drain Extended FinFETs”. EOS/ESD Symposium 2018, Reno, Nevada, USA.
  • B. S. Kumar, M. Paul, H. Gossner and M. Shrivastava. “Physical Insights, challenges & device design of high voltage (>5V) drain extended FinFET transistors”. (under submission) in IEEE Transactions on Electron Devices.
  • B. S. Kumar, M. Paul, H. Gossner and M. Shrivastava. “Electrostatic Discharge & Hot carrier reliability of High Voltage Drain extended FinFET transistors”. (under submission) in IEEE Transactions on Electron Devices.
  • B. S. Kumar, M. Paul, H. Gossner and M. Shrivastava. “Device design, performance and reliability insights of ultra high voltage (UHV) LDMOS transistors”. (under submission) in IEEE Transactions on Electron Devices.
  • M. Paul, B. S. Kumar, K. K. Nagothu, P. Singhal, H. Gossner and M. Shrivastava, “Novel SCR ESD Protection Concepts in Drain Extended Devices for Bulk FinFET Technologies”. (under submission) in IEEE Transactions on Electron Devices.
  • M. Paul, B. S. Kumar, H. Gossner and M. Shrivastava, “Hybrid Contact & Junction Engineering in Bulk FinFET Technology for improved ESD/Latch-Up Performance and HCI Reliability”. (under submission) in IEEE Transactions on Electron Devices.
  • M. Paul, B. S. Kumar, H. Gossner and M. Shrivastava, “ESD and HCI Behavior of Stacked Bulk FinFETs”.

(under submission) in IEEE Transactions on Electron Devices.

  • M. Paul, B. S. Kumar, H. Gossner and M. Shrivastava, “Multifin aspects in FinFET Technology: Impact of design and layout parameters”. (under submission) in IEEE Transactions on Electron Devices.
  • M. Paul, B. S. Kumar, H. Gossner and M. Shrivastava, “ESD and HCI exploration of Silicon-Germanium Heterojunction FinFETs”. (under submission) in IEEE Transactions on Electron Devices.

Patents

  • M. Paul, M. Shrivastava, B. S. Kumar, C. Russ and H. Gossner, “Dual Fin Silicon Controlled Rectifier (SCR) Electrostatic Discharge (ESD) Protection Device”. US Patent Pending, Application No: 15/883,306, Filed on: 30-Jan-18 (Indian Patent, Application No 201741003771, Filed on 1st Feb. 2017).

Awards:

  • Outstanding Paper Award, EOS/ESD Symposium, Sept
  • Honorable Mention Research Paper Award, VLSI Design Conference, Jan 2017